dp83630sqx National Semiconductor Corporation, dp83630sqx Datasheet - Page 7

• Manufacturer Part Number: dp83630sqx
• Description: Precision Phyter - Ieee 1588 Precision Time Protocol Transceiver
• Manufacturer: National Semiconductor Corporation

6.1 IEEE 1588 SYNCHRONIZED CLOCK
The DP83630 provides several mechanisms for updating the
IEEE 1588 clock based on the synchronization protocol re-
quired. These methods are listed below.
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The clock consists of the following fields: Seconds (32–bit
field), Nanoseconds (30–bit field), and Fractional Nanosec-
onds (units of 2
A direct set of the time value can be done by setting a new
time value. A step adjustment value in nanoseconds may be
added to the current value. Note that the adjustment value
can be positive or negative.
The clock can be programmed to operate at an adjusted fre-
quency value by programming a rate adjustment value. The
clock can also be programmed to perform a temporary ad-
justed frequency value by including a rate adjustment dura-
tion. The rate adjustment allows for correction on the order of
2
will allow the clock to correct the offset over time, avoiding any
potential side-effects caused by a step adjustment in the time
value.
The method used to update the clock value may depend on
the difference in the values. For example, at the initial syn-
chronization attempt, the clocks may be very far apart, and
-32
Directly Read/Writable
Adjustable by Add/Subtract
Frequency Scalable
Temporary Frequency Control
ns per reference clock cycle. The frequency adjustment
-32
ns).
FIGURE 1. DP83630 Example System Application
7
therefore require a step adjustment or a direct time set. Later,
when clocks are very close in value, the temporary rate ad-
justment method may be the best option.
The clock does not support negative time values. If negative
time is required in the system, software will have to make
conversions from the PHY clock time to actual time.
The clock also does not support the upper 16-bits of the sec-
onds field as defined by the specification (Version 2 specifies
a 48-bit seconds field). If this value is required to be greater
than 0, it will have to be handled by software. Since a rollover
of the seconds field only occurs every 136 years, it should not
be a significant burden to software.
6.1.1 IEEE 1588 Clock Output
The DP83630 provides for a synchronized clock signal for use
by external devices. The output clock signal can be any fre-
quency generated from 250 MHz divided by n, where n is an
integer in the range of 2 to 255. This provides nominal fre-
quencies from 125 MHz down to 980.4 kHz. The clock output
signal is controlled by the PTP_COC register. The output
clock signal is generated using the rate information in the
PTP_RATE registers and is therefore frequency accurate to
the 1588 clock time of the device. In addition, if clock time
adjustments are made using the Temporary Rate capabilities,
then all time adjustments will be tracked by the output clock
signal as well. Note that any step adjustment in the 1588 clock
time will not be accurately represented on the 1588 clock out-
put signal.
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