dp83630sqx National Semiconductor Corporation, dp83630sqx Datasheet - Page 107

• Manufacturer Part Number: dp83630sqx
• Description: Precision Phyter - Ieee 1588 Precision Time Protocol Transceiver
• Manufacturer: National Semiconductor Corporation

T2.5.1
T2.5.2
T2.6.1
Parameter
Parameter
18.2.5 100 Mb/s MII Receive Timing
Note: RX_CLK may be held low or high for a longer period of time during transition between reference and recovered clocks. Minimum high and low times will
18.2.6 100BASE-TX and 100BASE-FX MII Transmit Packet Latency Timing
Note: For Normal mode, latency is determined by measuring the time from the first rising edge of TX_CLK occurring after the assertion of TX_EN to the first bit
Note: Enabling PHY Control Frames will add latency equal to 8 bits times the PCF_BUF_SIZE setting. For example if PCF_BUF_SIZE is set to 15, then the
not be violated.
of the “J” code group as output from the PMD Output Pair. 1 bit time = 10 ns in 100 Mb/s mode.
additional delay will be 15*8 = 120 bits.
TX_CLK to PMD Output Pair Latency
RX_CLK High/Low Time
RX_CLK to RXD[3:0], RX_DV, RX_ER
Delay
Description
Description
100BASE-TX and 100BASE-FX modes
IEEE 1588 One-Step Operation enabled
100 Mb/s Normal mode
100 Mb/s Normal mode
107
Notes
Notes
Min
16
10
Min
Typ
20
30136225
Typ
5
9
30136224
Max
24
30
Max
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Units
Units
ns
ns
bits
bits