dp83630sqx National Semiconductor Corporation, dp83630sqx Datasheet - Page 18

• Manufacturer Part Number: dp83630sqx
• Description: Precision Phyter - Ieee 1588 Precision Time Protocol Transceiver
• Manufacturer: National Semiconductor Corporation

www.national.com
9.0 Configuration
This section includes information on the various configuration
options available with the DP83630. The configuration op-
tions described below include:
— Media Configuration
— Auto-Negotiation
— PHY Address and LEDs
— Half Duplex vs. Full Duplex
— Isolate mode
— Loopback mode
— BIST
9.1 MEDIA CONFIGURATION
The DP83630 supports both Twister Pair (100BASE-TX and
10BASE-T) and Fiber (100BASE-FX) media. The port may be
configured for Twisted Pair (TP) or Fiber (FX) operation by
strap option or by register access.
At power-up/reset, the state of the RX_ER pin will select the
media for the port. The default selection is twisted pair mode,
while an external pull-down will select FX mode of operation.
Strapping the port into FX mode also automatically sets the
Far-End Fault Enable, bit 3 of PCSR (16h), the Scramble By-
pass, bit 1 of PCSR (16h) and the Descrambler Bypass, bit 0
of PCSR (16h). In addition, the media selection may be con-
trolled by writing to bit 6, FX_EN, of PCSR (16h).
9.2 AUTO-NEGOTIATION
The Auto-Negotiation function provides a mechanism for ex-
changing configuration information between two ends of a link
segment and automatically selecting the highest performance
mode of operation supported by both devices. Fast Link Pulse
(FLP) Bursts provide the signalling used to communicate Au-
to-Negotiation abilities between two devices at each end of a
link segment. For further detail regarding Auto-Negotiation,
refer to Clause 28 of the IEEE 802.3u specification. The
DP83630 supports four different Ethernet protocols (10 Mb/s
Half Duplex, 10 Mb/s Full Duplex, 100 Mb/s Half Duplex, and
100 Mb/s Full Duplex), so the inclusion of Auto-Negotiation
ensures that the highest performance protocol will be select-
ed based on the advertised ability of the Link Partner. The
Auto-Negotiation function within the DP83630 can be con-
trolled either by internal register access or by the use of the
AN_EN, AN1 and AN0 pins.
9.2.1 Auto-Negotiation Pin Control
The state of AN_EN, AN0 and AN1 determines whether the
DP83630 is forced into a specific mode or Auto-Negotiation
will advertise a specific ability (or set of abilities) as given in
Table
without requiring internal register access.
The state of AN_EN, AN0 and AN1, upon power-up/reset,
determines the state of bits [8:5] of the ANAR register.
The Auto-Negotiation function selected at power-up or reset
can be changed at any time by writing to the Basic Mode
Control Register (BMCR) at address 00h.
1. These pins allow configuration options to be selected
18
9.2.2 Auto-Negotiation Register Control
When Auto-Negotiation is enabled, the DP83630 transmits
the abilities programmed into the Auto-Negotiation Advertise-
ment register (ANAR) at address 04h via FLP Bursts. Any
combination of 10 Mb/s, 100 Mb/s, Half-Duplex, and Full Du-
plex modes may be selected.
Auto-Negotiation Priority Resolution:
1.
2.
3.
4.
The Basic Mode Control Register (BMCR) at address 00h
provides control for enabling, disabling, and restarting the
Auto-Negotiation process. When Auto-Negotiation is dis-
abled, the SPEED SELECTION bit in the BMCR controls
switching between 10 Mb/s or 100 Mb/s operation, and the
DUPLEX MODE bit controls switching between full duplex
operation and half duplex operation. The SPEED SELEC-
TION and DUPLEX MODE bits have no effect on the mode
of operation when the Auto-Negotiation Enable bit is set.
The Link Speed can be examined through the PHY Status
Register (PHYSTS) at address 10h after a Link is achieved.
The Basic Mode Status Register (BMSR) indicates the set of
available abilities for technology types, Auto-Negotiation abil-
ity, and Extended Register Capability. These bits are perma-
nently set to indicate the full functionality of the DP83630 (only
the 100BASE-T4 bit is not set since the DP83630 does not
support that function).
The BMSR also provides status on:
•
•
•
•
The Auto-Negotiation Advertisement Register (ANAR) indi-
cates the Auto-Negotiation abilities to be advertised by the
DP83630. All available abilities are transmitted by default, but
any ability can be suppressed by writing to the ANAR. Up-
dating the ANAR to suppress an ability is one way for a
management agent to change (restrict) the technology that is
used.
The Auto-Negotiation Link Partner Ability Register (ANLPAR)
at address 05h is used to receive the base link code word as
well as all next page code words during the negotiation. Fur-
thermore, the ANLPAR will be updated to either 0081h or
0021h for parallel detection to either 100 Mb/s or 10 Mb/s re-
spectively.
AN_EN
AN_EN
Whether or not Auto-Negotiation is complete
Whether or not the Link Partner is advertising that a
remote fault has occurred
Whether or not valid link has been established
Support for Management Frame Preamble suppression
100BASE-TX Full Duplex (Highest Priority)
100BASE-TX Half Duplex
10BASE-T Full Duplex
10BASE-T Half Duplex (Lowest Priority)
0
0
0
0
1
1
1
1
TABLE 1. Auto-Negotiation Modes
AN1 AN0
AN1 AN0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
10BASE-T, Half-Duplex
10BASE-T, Full-Duplex
100BASE-TX, Half-Duplex
100BASE-TX, Full-Duplex
10BASE-T, Half/Full-Duplex
100BASE-TX, Half/Full-Duplex
100BASE-TX Full-Duplex
10BASE-T, Half/Full-Duplex
100BASE-TX, Half/Full-Duplex
Advertised Mode
Forced Mode