dp83630sqx National Semiconductor Corporation, dp83630sqx Datasheet - Page 100

• Manufacturer Part Number: dp83630sqx
• Description: Precision Phyter - Ieee 1588 Precision Time Protocol Transceiver
• Manufacturer: National Semiconductor Corporation

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15:14
15:8
15:4
13:7
15:0
Bit
7:4
3:0
Bit
3:0
Bit
6:0
Bit
14.7.6 PTP SFD Configuration Register (PTP_SFDCFG), Page 6
This register provides configuration to enable outputting the RX and TX Start-of-Frame (SFD) signals on GPIO pins. Note that
GPIO assignments are not exclusive.
14.7.7 PTP Interrupt Control Register (PTP_INTCTL), Page 6
This register provides configuration for the IEEE 1588 interrupt function, allowing the PTP Interrupt to use any of the GPIO pins.
14.7.8 PTP Clock Source Register (PTP_CLKSRC), Page 6
This register provides configuration for the reference clock source driving the IEEE 1588 logic. The source clock period is also
used by the 1588 clock nanoseconds adder to add the proper value every reference clock cycle.
14.7.9 PTP Ethernet Type Register (PTP_ETR), Page 6
This register provides the Ethernet Type (Ethertype) field for PTP transport over Ethernet (Layer2).
PTP_INT_GPIO
CLK_SRC_PER
RX_SFD_GPIO
TX_SFD_GPIO
PTP_ETYPE
RESERVED
RESERVED
RESERVED
CLK_SRC
Bit Name
Bit Name
Bit Name
Bit Name
TABLE 80. PTP SFD Configuration Register (PTP_SFDCFG), address 0x19
TABLE 81. PTP Interrupt Control Register (PTP_INTCTL), address 0x1A
TABLE 82. PTP Clock Source Register (PTP_CLKSRC), address 0x1B
TABLE 83. PTP Ethernet Type Register (PTP_ETR), address 0x1C
0000 0000 0000,
1111 0111 1000
0000 0000, RO
00 0000 0, RO
000 0000, RW
0000, RW
0000, RW
0000, RW
1000, RW
Default
Default
Default
00, RW
Default
RO
Reserved: Writes ignored, Read as 0
TX SFD GPIO Select:
This field controls the GPIO output to which the TX SFD signal is assigned. Valid
values are 0 (disabled) or 1-12.
RX SFD GPIO Select:
This field controls the GPIO output to which the RX SFD signal is assigned. Valid
values are 0 (disabled) or 1-12.
Reserved: Writes ignored, Read as 0
PTP Interrupt GPIO Select:
To enable interrupts on a GPIO pin, this field should be set to the GPIO number.
Setting this field to 0 will disable interrupts via the GPIO pins.
PTP Clock Source Select:
Selects among three possible sources for the PTP reference clock:
00 : 125 MHz from internal PGM (default)
01 : Divide-by-N from 125 MHz internal PGM
1x : External reference clock
Reserved: Writes ignored, Read as 0
PTP Clock Source Period:
This field configures the PTP clock source period in nanoseconds. Values less
than 8 are invalid and cannot be written; attempting to write a value less than 8
will cause CLK_SRC_PER to be 8. When the clock source selection is the Divide-
by-N from the internal PGM, bits 6:3 are used as the N value; bits 2:0 are ignored
in this mode.
PTP Ethernet Type:
This field contains the Ethernet Type field used to detect PTP messages
transported over Ethernet layer 2.
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Description
Description
Description
Description