dp83630sqx National Semiconductor Corporation, dp83630sqx Datasheet - Page 10

• Manufacturer Part Number: dp83630sqx
• Description: Precision Phyter - Ieee 1588 Precision Time Protocol Transceiver
• Manufacturer: National Semiconductor Corporation

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MDC
MDIO
TX_CLK
TX_EN
TXD_0
TXD_1
TXD_2
TXD_3
RX_CLK
8.0 Pin Descriptions
The DP83630 pins are classified into the following interface
categories (each interface is described in the sections that
follow):
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•
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Note: Strapping pin option. Please see Section
8.1 SERIAL MANAGEMENT INTERFACE
8.2 MAC DATA INTERFACE
Signal Name
Signal Name
Serial Management Interface
MAC Data Interface
Clock Interface
LED Interface
GPIO Interface
JTAG Interface
Reset and Power Down
Strap Options
10/100 Mb/s PMD Interface
Power and Ground pins
TIONSfor strap definitions.
MDC
MDIO
TX_CLK
TX_EN
TXD_0
TXD_1
TXD_2
TXD_3
RX_CLK
Pin Name
Pin Name
Section 8.8 STRAP OP-
Type
Type
I, PD
I, PD
I/O
O
O
I
I
I
I
Pin #
Pin #
31
30
38
1
2
3
4
5
6
MANAGEMENT DATA CLOCK: Synchronous clock to the MDIO
management data input/output serial interface which may be
asynchronous to transmit and receive clocks. The maximum clock rate is
25 MHz with no minimum clock rate.
MANAGEMENT DATA I/O: Bi-directional management instruction/data
signal that may be sourced by the station management entity or the PHY.
This pin requires a 1.5 kΩ pullup resistor. Alternately, an internal pullup
may be enabled by setting bit 3 in the CDCTRL1 register.
MII TRANSMIT CLOCK: 25 MHz Transmit clock output in 100 Mb/s mode
or 2.5 MHz in 10 Mb/s mode derived from the 25 MHz reference clock.
The MAC should source TX_EN and TXD[3:0] using this clock.
RMII MODE: Unused in RMII Slave mode. The device uses the X1
reference clock input as the 50 MHz reference for both transmit and
receive. For RMII Master mode, the device outputs the internally
generated 50 MHz reference clock on this pin.
This pin provides an integrated 50 ohm signal termination, making
external termination resistors unnecessary.
MII TRANSMIT ENABLE: Active high input indicates the presence of
valid data inputs on TXD[3:0].
RMII TRANSMIT ENABLE: Active high input indicates the presence of
valid data on TXD[1:0].
MII TRANSMIT DATA: Transmit data MII input pins, TXD[3:0], that
accept data synchronous to the TX_CLK (2.5 MHz in 10 Mb/s mode or
25 MHz in 100 Mb/s mode).
RMII TRANSMIT DATA: Transmit data RMII input pins, TXD[1:0], that
accept data synchronous to the 50 MHz reference clock.
MII RECEIVE CLOCK: Provides the 25 MHz recovered receive clocks
for 100 Mb/s mode and 2.5 MHz for 10 Mb/s mode.
RMII MODE: Unused in RMII Slave mode. The device uses the X1
reference clock input as the 50 MHz reference for both transmit and
receive. For RMII Master mode, the device outputs the internally
generated 50 MHz reference clock on this pin.
This pin provides an integrated 50 ohm signal termination, making
external termination resistors unnecessary.
10
All DP83630 signal pins are I/O cells regardless of the par-
ticular use. The definitions below define the functionality of
the I/O cells for each pin.
Type: I
Type: O
Type: I/O
Type: OD
Type: PD
Type: PU
Type: S
Input
Output
Input/Output
Open Drain
Internal Pulldown
Internal Pullup
Strapping Pin (All strap pins have weak
internal pull-ups or pull-downs. If the default
strap value is to be changed then an external
2.2 kΩ resistor should be used. Please see
Section
details.)
Description
Description
Section 8.8 STRAP OPTIONS
for