dp83630sqx National Semiconductor Corporation, dp83630sqx Datasheet - Page 22

• Manufacturer Part Number: dp83630sqx
• Description: Precision Phyter - Ieee 1588 Precision Time Protocol Transceiver
• Manufacturer: National Semiconductor Corporation

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Auto-Negotiation is not supported in 100BASE-FX operation.
Selection of Half or Full-duplex operation is controlled by bit
8 of the Basic Mode Control Register (BMCR), address 00h.
If 100BASE-FX mode is strapped using the RX_ER pin, the
AN0 strap value is used to set the value of bit 8 of the BMCR
(00h) register. Note that the other Auto-Negotiation strap pins
(AN_EN and AN1) are ignored in 100BASE-FX mode.
9.8 INTERNAL LOOPBACK
The DP83630 includes a Loopback Test mode for facilitating
system diagnostics. The Loopback mode is selected through
bit 14 (Loopback) of the Basic Mode Control Register (BM-
CR). Writing 1 to this bit enables MII transmit data to be routed
to the MII receive outputs. Loopback status may be checked
in bit 3 of the PHY Status Register (PHYSTS). While in Loop-
back mode the data will not be transmitted onto the media. To
ensure that the desired operating mode is maintained, Auto-
Negotiation should be disabled before selecting the Loopback
mode.
9.9 POWER DOWN/INTERRUPT
The Power Down and Interrupt functions are multiplexed on
pin 7 of the device. By default, this pin functions as a power
down input and the interrupt function is disabled. Setting bit 0
(INT_OE) of MICR (11h) will configure the pin as an active
low interrupt output.
9.9.1 Power Down Control Mode
The PWRDOWN/INTN pin can be asserted low to put the de-
vice in a Power Down mode. This is equivalent to setting bit
11 (POWER DOWN) in the Basic Mode Control Register,
BMCR (00h). An external control signal can be used to drive
the pin low, overcoming the weak internal pull-up resistor. Al-
ternatively, the device can be configured to initialize into a
Power Down state by use of an external pull-down resistor on
the PWRDOWN/INTN pin. Since the device will still respond
to management register accesses, setting the INT_OE bit in
the MICR register will disable the PWRDOWN/INTN input,
allowing the device to exit the Power Down state.
9.9.2 Interrupt Mechanisms
The interrupt function is controlled via register access. All in-
terrupt sources are disabled by default. Setting bit 1 (INTEN)
of MICR (11h) will enable interrupts to be output, dependent
on the interrupt mask set in the lower byte of the MISR (12h).
The PWRDOWN/INTN pin is asynchronously asserted low
when an interrupt condition occurs. The source of the interrupt
can be determined by reading the upper byte of the MISR.
One or more bits in the MISR will be set, denoting all currently
pending interrupts. Reading of the MISR clears ALL pending
interrupts.
Example: To generate an interrupt on a change of link status
or on a change of energy detect power state, the steps would
be:
•
•
•
When PWRDOWN/INTN pin asserts low, the user would read
the MISR register to see if the ED_INT or LINK_INT bits are
set, i.e. which source caused the interrupt. After reading the
MISR, the interrupt bits should clear and the PWRDOWN/
INTN pin will de-assert.
9.10 ENERGY DETECT MODE
When Energy Detect is enabled and there is no activity on the
cable, the DP83630 will remain in a low power mode while
Write 0003h to MICR to set INTEN and INT_OE
Write 0060h to MISR to set ED_INT_EN and
LINK_INT_EN
Monitor PWRDOWN/INTN pin
22
monitoring the transmission line. Activity on the line will cause
the DP83630 to go through a normal power up sequence.
Regardless of cable activity, the DP83630 will occasionally
wake up the transmitter to put ED pulses on the line, but will
otherwise draw as little power as possible. Energy detect
functionality is controlled via register Energy Detect Control
(EDCR), address 1Dh.
9.11 LINK DIAGNOSTIC CAPABILITIES
The DP83630 contains several system diagnostic capabilities
for evaluating link quality and detecting potential cabling faults
in twisted pair cabling. Software configuration is available
through the Link Diagnostics Registers - Page 2 which can be
selected via Page Select Register (PAGESEL), address 13h.
These capabilities include:
— Linked Cable Status
— Link Quality Monitor
— TDR (Time Domain Reflectometry) Cable Diagnostics
9.11.1 Linked Cable Status
In an active connection with a valid link status, the following
diagnostic capabilities are available:
— Polarity reversal
— Cable swap (MDI vs MDIX) detection
— 100 Mb Cable Length Estimation
— Frequency offset relative to link partner
— Cable Signal Quality Estimation
9.11.1.1 Polarity Reversal
The DP83630 detects polarity reversal by detecting negative
link pulses. The Polarity indication is available in bit 12 of the
PHYSTS (10h) or bit 4 of the 10BTSCR (1Ah). Inverted po-
larity indicates the positive and negative conductors in the
receive pair are swapped. Since polarity is corrected by the
receiver, this does not necessarily indicate a functional prob-
lem in the cable.
Since the polarity indication is dependent on link pulses from
the link partner, polarity indication is only valid in 10 Mb modes
of operation, or in 100 Mb Auto-Negotiated mode. Polarity in-
dication is not available in 100 Mb forced mode of operation
or in a parallel detected 100 Mb mode.
9.11.1.2 Cable Swap Indication
As part of Auto-Negotiation, the DP83630 has the ability (us-
ing Auto-MDIX) to automatically detect a cable with swapped
MDI pairs and select the appropriate pairs for transmitting and
receiving data. Normal operation is termed MDI, while
crossed operation is MDIX. The MDIX status can be read from
bit 14 of the PHYSTS (10h).
9.11.1.3 100 Mb Cable Length Estimation
The DP83630 provides a method of estimating cable length
based on electrical characteristics of the 100 Mb link. This
essentially provides an effective cable length rather than a
measurement of the physical cable length. The cable length
estimation is only available in 100 Mb mode of operation with
a valid link status. The cable length estimation is available at
the Link Diagnostics Registers - Page 2, register 100 Mb
Length Detect (LEN100_DET), address 14h.
9.11.1.4 Frequency Offset Relative to Link Partner
As part of the 100 Mb clock recovery process, the DSP im-
plementation provides a frequency control parameter. This
value may be used to indicate the frequency offset of the de-
vice relative to the link partner. This operation is only available
in 100 Mb operation with a valid link status. The frequency