dp83630sqx National Semiconductor Corporation, dp83630sqx Datasheet - Page 33

• Manufacturer Part Number: dp83630sqx
• Description: Precision Phyter - Ieee 1588 Precision Time Protocol Transceiver
• Manufacturer: National Semiconductor Corporation

11.2.4 MLT-3 to Binary Decoder
The DP83630 decodes the MLT-3 information from the Digital
Adaptive Equalizer block to binary NRZI data.
11.2.5 Clock Recovery Module
The Clock Recovery function is implemented as a Phase de-
tector and Loop Filter which accepts data and error from the
receive datapath to detect the phase of the recovered data.
This phase information is fed into the loop filter to determine
an 8-bit signed frequency control. The 8-bit signed frequency
control is sent to the FCO in the Analog Front End to derive
the receive clock. The extracted and synchronized clock and
data are used as required by the synchronous receive oper-
ations as generally depicted in
11.2.6 NRZI to NRZ Decoder
In a typical application, the NRZI to NRZ decoder is required
in order to present NRZ formatted data to the descrambler (or
to the code-group alignment block if the descrambler is by-
passed).
11.2.7 Serial to Parallel
The 100BASE-TX receiver includes a Serial to Parallel con-
verter which supplies 5-bit wide data symbols to the PCS Rx
state machine.
11.2.8 Descrambler
A serial descrambler is used to de-scramble the received NRZ
data. The descrambler has to generate an identical data
scrambling sequence (N) in order to recover the original un-
scrambled data (UD) from the scrambled data (SD) as rep-
resented in the equations:
Synchronization of the descrambler to the original scrambling
sequence (N) is achieved based on the knowledge that the
incoming scrambled data stream consists of scrambled IDLE
data. After the descrambler has recognized 12 consecutive
IDLE code-groups, where an unscrambled IDLE code-group
in 5B NRZ is equal to five consecutive ones (11111), it will
synchronize to the receive data stream and generate un-
scrambled data in the form of unaligned 5B code-groups.
In order to maintain synchronization, the descrambler must
continuously monitor the validity of the unscrambled data that
it generates. To ensure this, a line state monitor and a hold
timer are used to constantly monitor the synchronization sta-
tus. Upon synchronization of the descrambler, the hold timer
starts a 722 µs countdown. Upon detection of sufficient IDLE
code-groups (58 bit times) within the 722 µs period, the hold
timer will reset and begin a new countdown. This monitoring
operation will continue indefinitely given a properly operating
network connection with good signal integrity. If the line state
monitor does not recognize sufficient unscrambled IDLE
code-groups within the 722 µs period, the entire descrambler
will be forced out of the current state of synchronization and
reset in order to re-acquire synchronization. The DP83604T
also provides a bit (DESC_TIME, bit 7) in the PCSR register
(0x16) that increases the descrambler timeout from 722 µs to
2 ms to allow reception of packets up to 9kB in size without
losing descrambler lock.
11.2.9 Code-Group Alignment
The code-group alignment module operates on unaligned 5-
bit data from the descrambler (or, if the descrambler is by-
Figure
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7.
33
passed, directly from the NRZI/NRZ decoder) and converts it
into 5B code-group data (5 bits). Code-group alignment oc-
curs after the J/K code-group pair is detected. Once the J/K
code-group pair (11000 10001) is detected, subsequent data
is aligned on a fixed boundary.
11.2.10 4B/5B Decoder
The code-group decoder functions as a look up table that
translates incoming 5B code-groups into 4B nibbles. The
code-group decoder first detects the J/K code-group pair pre-
ceded by IDLE code-groups and replaces the J/K with MAC
preamble. Specifically, the J/K 10-bit code-group pair is re-
placed by the nibble pair (0101 0101). All subsequent 5B
code-groups are converted to the corresponding 4B nibbles
for the duration of the entire packet. This conversion ceases
upon the detection of the T/R code-group pair denoting the
End of Stream Delimiter (ESD) or with the reception of a min-
imum of two IDLE code-groups.
11.2.11 100BASE-TX Link Integrity Monitor
The 100BASE-TX link monitor ensures that a valid and stable
link is established before enabling both the Transmit and Re-
ceive PCS layer.
Signal detect must be valid for 395 µs to allow the link monitor
to enter the 'Link Up' state and enable the transmit and receive
functions.
11.2.12 Bad SSD Detection
A Bad Start of Stream Delimiter (Bad SSD) is any transition
from consecutive idle code-groups to non-idle code-groups
which is not prefixed by the code-group pair /J/K.
If this condition is detected, the DP83630 will assert RX_ER
and present RXD[3:0] = 1110 to the MII for the cycles that
correspond to received 5B code-groups until at least two IDLE
code-groups are detected. In addition, the False Carrier
Sense Counter register (FCSCR) will be incremented by one.
Once at least two IDLE code-groups are detected, RX_ER
and CRS become de-asserted.
11.3 100BASE-FX OPERATION
The DP83630 provides IEEE 802.3 compliant 100BASE-FX
operation. Configuration of FX mode is via strap option, or
through the register interface.
11.3.1 100BASE-FX Transmit
In 100BASE-FX mode, the device Transmit pins connect to
an industry standard Fiber Transceiver with PECL signaling
through a capacitively coupled circuit.
In FX mode, the device bypasses the Scrambler and the
MLT3 encoder. This allows for the transmission of serialized
5B4B encoded NRZI data at 125 MHz.
The only added functionality from 100BASE-TX is the support
for Far-End Fault data generation.
11.3.2 100BASE-FX Receive
In 100BASE-FX mode, the device Receive pins connect to an
industry standard Fiber Transceiver with PECL signaling
through a capacitively coupled circuit.
In FX mode, the device bypasses the MLT3 Decoder and the
Descrambler. This allows for the reception of serialized 5B4B
encoded NRZI data at 125 MHz.
The only added functionality for 100BASE-FX from
100BASE-TX is the support of Far-End Fault detection.
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