ml7084-001 Oki Semiconductor, ml7084-001 Datasheet - Page 202

• Manufacturer Part Number: ml7084-001
• Description: 4ch Voip Codec
• Manufacturer: Oki Semiconductor

C. DPGEN0 speed control register (DPGEN0_PPS)
D. DPGEN0 output polarity control register (DPGEN0_POL)
E. Internal data memory for DPGEN0 make ratio control (DPGEN0_DUTY)
F. Internal data memory for DPGEN0 output end control (DPGEN0_OFF_TIM)
OKI Semiconductor
0 : 10 pps (Initial value)
1 : 20 pps
0
1
Initial value : 0108h(33ms/10 pps, 16.5 ms/20 pps)
To set the time of the break interval, use the following formula:
For 20 pps, the time is a half of this setting value.
Equation: Break interval output time in ms/0.125 ms
Example: 33 ms
33/0.125 = 264d = 0108h
Initial value : 03E8h(125 ms)
Use the following equation when controlling the end of output.
Equation: Output end time in ms/0.125 ms
Example: 125 ms
125/0.125 = 1000d = 03E8h
(Note) Before activating DPGEN0 (DPGEN0_EN=1), be sure to set the following:
Upper limit : 100 ms
Lower limit : 0.125 ms
Upper limit : 4095.875 ms
Lower limit : 0 ms
Positive logic (Low: Make interval, High: Break interval), Initial value
Negative logic (Low: Break interval, High: Make interval)
• Set the DPGEN0 output polarity control register (DPGEN0_POL).
• After the above setting, set the primary/secondary function selection register of GPIOA[0]
By this setting, the output level (initial value) of the dial pulse output pin will be as follows:
(GPFA[0]) to “1” to select the secondary function (dial pulse output pin).
When DPGEN0_POL = 0 (positive logic) : GPOA[0]/DPO0 = “0”
When DPGEN0_POL = 1 (negative logic) : GPOA[0]/DPO0 = “1”
: 33 ms
: 125 ms
(data: 0320h)
(data: 0108h)
(data: 0001h)
(data: 7FFFh)
(data: 03E8h)
(data: 0000h)
FEDL7224-001FULL-01
ML7224-001TC
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