ml7084-001 Oki Semiconductor, ml7084-001 Datasheet - Page 29

• Manufacturer Part Number: ml7084-001
• Description: 4ch Voip Codec
• Manufacturer: Oki Semiconductor

FEDL7224-001FULL-01
OKI Semiconductor
ML7224-001TC
AIN0N_a, AIN0P_a, GSX0_a
Transmission analog input and transmission level adjustment pins for CH0a. AIN0N_a is connected to the inverting
input pin of the internal transmit amplifier, and AIN0P_a is connected to the non-inverting input pin. GSX0_a is
conneced to the output pin of the internal transmit amplifier. For more information about level adjustment, see
Figure 10.
At hardware power down (PDNB = “0”), or in a reset state on the DSP_A side (DSP_RESET_a = “1”), the output of
GSX0_a will be placed in a high impedance state. Since the use of an analog interface is prohibited in this code,
short GSX0_a and AIN0N_a, and connect AIN0P_a with AVREF.
VFRO0_a
Reception analog output pin for CH0a. VFRO0_a is connected to the output pin of the internal receive amplifier. For
the output signal of VFRO0_a, output can be selected with the VFRO0 selection register_a (VFRO0_SEL_a). When
selected (“1”), a reception signal is output; when unselected (“0”), AVREF (approximately 1.4 V) is output. At
hardware power down (PDNB = “0”), or in a reset state on the DSP_A side (DSP_RESET_a = “1”), the output of
this pin will be placed in a high impedance state. It is recommended to use the output signal via a capacitor for DC
coupling.
Because the use of an analog interface is prohibited in this code, leave this pin open.
Note:
If output selection is changed during a call, minor noise will be generated. Therefore, it is recommended to select an
output before starting a call, and then start a call after output selection. When canceling a reset or resetting, it is
recommended to do so with the output of VFRO0_a selected to the AVREF output side.
AIN1N_a, AIN1P_a, GSX1_a
Transmission analog input and transmission level adjustment pins for CH1a. AIN1N_a is connected to the inverting
input pin of the internal transmit amplifier, and AIN1P_a is connected to the non-inverting input pin. GSX1_a is
conneced to the output pin of the internal transmit amplifier. For more information about level adjustment, see
Figure 10.
At hardware power down (PDNB = “0”), or in a reset state on the DSP_A side (DSP_RESET_a = “1”), the output of
GSX1_a will be placed in a high impedance state. Since the use of an analog interface is prohibited in this code,
short GSX1_a and AIN1N_a, and connect AIN1P_a with AVREF.
VFRO1_a
Reception analog output pin for CH1a. VFRO1_a is connected to the output pin of the internal receive amplifier. For
the output signal of VFRO1_a, output can be selected with the VFRO1 selection register_a (VFRO1_SEL_a). When
selected (“1”), a reception signal is output; when unselected (“0”), AVREF (approximately 1.4 V) is output. At
hardware power down (PDNB = “0”), or in a reset state on the DSP_A side (DSP_RESET_a = “1”), the output of
this pin will be placed in a high impedance state. It is recommended to use the output signal via a capacitor for DC
coupling.
Because the use of an analog interface is prohibited in this code, leave this pin open.
Note:
If output selection is changed during a call, minor noise will be generated. Therefore, it is recommended to select an
output before starting a call. When canceling a reset or resetting, it is recommended to do so with the output of
VFRO1_a selected to the AVREF output side.
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