ml7084-001 Oki Semiconductor, ml7084-001 Datasheet - Page 88

• Manufacturer Part Number: ml7084-001
• Description: 4ch Voip Codec
• Manufacturer: Oki Semiconductor

B7: Initial mode indication register
(5) CR5
B6 : Download circuit status notification register 2
B5 : Download circuit status notification register 1
B4 : Download circuit status notification register 0
B3–B1 : Reserved bits.
B0 : Receive data write channel notification register
OKI Semiconductor
setting can be
Mode where
Initial value
Once the downloading of the DSP firmware is completed normally, the mode enters the initial mode. This bit
will be set to “1” in the initial mode.
0: Other than the initial mode
1: Initialization in progress
0 : PRAM write normally ended
1 : PRAM write error occurred
By reading this register when the download circuit status notification register 0 (DL_ST0) is “1”, whether a
write to PRAM has been compelted normally or not can be checked. Note that when the download circuit status
notification register 0 (DL_ST0) is “0”, the value of this register is invalid.
0 : DRAM write normally ended
1 : DRAM write error occurred
By reading this register when the download circuit status notification register 0 (DL_ST0) is “1”, whether a
write to DRAM has been compelted normally or not can be checked. Note that when the download circuit status
notification register 0 (DL_ST0) is “0”, the value of this register is invalid.
0 : Does not notify status.
1 : Notifies status.
This bit is set to “1” when notifying whether or not the writing of data to PRAM/DRAM has been completed
normally. Read the download circuit status notification register 1 (DL_ST1) or the download circuit status
notification register 2 (DL_ST2) while this bit is “1”.
Note:
Write error check performed by this LSI never can detect all write errors.
While requesting 2-channel reception (RXREQ_DC=1), two reception requests will be made within one frame.
Write the receive data of channel 0 or 1 for every reception request. There is no specification as to the order of
writing. Notify the channel of receive data to the LSI by setting RXFLAG to one of the following before writing
receive data:
“0”
“1”
changed
CR5
: Notifies the writing of receive data of channel 0.
: Notifies the writing of receive data of channel 1.
READY
B7
⎯
0
Do not change the initial values.
ST2
DL_
B6
⎯
0
DL_
ST1
B5
⎯
0
DL_
ST0
B4
⎯
0
B3
⎯
#
0
B2
⎯
#
0
B1
⎯
#
0
FEDL7224-001FULL-01
FLAG
ML7224-001TC
RX_
B0
/E
0
R/W
R/W
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