ml7084-001 Oki Semiconductor, ml7084-001 Datasheet - Page 82

• Manufacturer Part Number: ml7084-001
• Description: 4ch Voip Codec
• Manufacturer: Oki Semiconductor

B7: TGEN1 TX section output control register
B6: TGEN1 RX section output control register
B5: Register for controlling addition or multiplication of TONE C/D
B4: TONE C/D output control register
B3, B2: TONE C output control registers
B1, B0: TONE D output control registers
(3) CR3
OKI Semiconductor
setting can be
Mode where
Initial value
Note:
It is prohibited to write any value into this register other than 00h when continuous output is being made.
In the case of single-tone output operation, make the next setting only after making sure that the content of this
To output again after stopping continuous outputs, set by allocating at least “FADE OUT time + 250 μs.”
Note:
Although it is possible to output TONE C and TONE D alternately when the output controls of TONE C and
To activate TGEN1, be sure to place FSKGEN1 and DPGEN1 in a stop state. It is not allowed to use TGEN1,
register has become 00h.
TONE D are set in a mutually exclusive manner and their outputs are summed, the waveform after addition will
be discontinuous since the phases of the two signals will be independent of each other.
FSKGEN1 and DPGEN1 simultaneously.
changed
CR3
0: Addition (The TONE C and TONE D outputs are added.)
1: Multiplication (The TONE C and TONE D outputs are multiplied.)
0: Stops output.
1: Outputs tone at the TX section.
0: Stops output.
1: Outputs tone at the RX section.
0: Single-tone output
1: Continuous tone output
00: No tone is output.
01: The tone is stopped during the M0 period and is output during the M1 period.
10: The tone is output during the M0 period and stopped during the M1 period.
11: The tone is output during both the M0 and M1 periods.
00: No tone is output.
01: The tone is stopped during the M0 period and is output during the M1 period.
10: The tone is output during the M0 period and is stopped during the M1 period.
11: The tone is output during both the M0 and M1 periods.
The signal is output repeatedly as controlled by the time duration equal to the sum of TIM_M0 and
To stop the signal output, set this register to 00h.
The signal is output for a duration equal to the sum of TIM_M0 and TIM_M1 and then stopped.
After stopping, this register will be cleared automatically inside the LSI.
TIM_M1.
TGEN1
_TX
B7
0
TGEN1
_RX
B6
0
TGEN1
_CNT5
B5
0
TGEN1
_CNT4
B4
0
I/E
TGEN1
_CNT3
B3
0
TGEN1
_CNT2
B2
0
TGEN1
_CNT1
B1
0
FEDL7224-001FULL-01
TGEN1
_CNT0
ML7224-001TC
B0
0
R/W
R/W
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