ml7084-001 Oki Semiconductor, ml7084-001 Datasheet - Page 218

• Manufacturer Part Number: ml7084-001
• Description: 4ch Voip Codec
• Manufacturer: Oki Semiconductor

Configuration Example 3 (three-way calling: two persons on the terminal side [CHa–CHb], one person on
the network side)
This configuration example shows a case of calling made by three persons: two persons (Mr. A and Mr. B) on the
terminal side, one person (Mr. C) on the network side.
This configuration example shows a case where two persons on the terminal side are connected to CH0a and CH0b.
To make a three-way calling in this configuration, control the speech path switch using the following settings:
R1_TXON_a (CR44a-B5) = 1, R1_RXON_a (CR44a-B4) = 1
R1_RXON_b (CR44b-B4) = 1, T0_TXON_a (CR44a-B3) = 1
OKI Semiconductor
VFRO0_ a
VFRO1_a
VFRO0_b
VFRO1_b
A
PCMO_ a
PCMO_b
AIN0N_a
AIN0P_a
AIN1N_a
AIN1P_a
AIN0N_b
AIN0P _b
AIN1N_b
AIN1P _b
CLKSEL
GSX 0_a
B
GSX 1_a
AVREF
GSX0 _b
GSX1 _b
PCMI_a
PCMI_b
B
SYNC
BCLK
XO
A
C
XI
C
AMP0Ra
AMP1Ra
AMP0Rb
AMP1Ra
12.288MHz
10 kΩ
10 kΩ
10 kΩ
10kΩ
VREF
OSC
S/P
P/S
AMP0 Ta
S /P
P /S
AMP1 Ta
10kΩ
10kΩ
10kΩ
10kΩ
AMP1Ta
AMP0Tb
pia
poa
pib
pob
pia
poa
pib
pob
VFRO0_SEL_a
VFRO1_SEL_a
VFRO0_SEL_b
VFRO1_SEL_b
OTS0_SEL_b
OTS1_SEL_b
OTS1_SEL_a
ITS1_SEL_a
ITS1_SEL_b
ITS0_SEL_a
OTS0_SEL_a
ITS0_SEL_b
PLL
ITS1Ub
ITS0Ua
ITS0La
OTS0Ua
ITS1Ua
ITS1La
OTS1Ua
OTS1La
ITS0Ub
ITS0Lb
OTS0Ub
ITS1Lb
OTS1Ub
OTS1Lb
OTS0La
OTS0Lb
PCM CODEC(CH0a)
PCM CODEC(CH1a)
PCM CODEC(CH1b)
CK
GN
PCM CODEC(CH0 b)
PCM_SEL[1:0]_a
CODEC(CH0a )
CODEC(CH1a)
CODEC(CH0b)
CODEC(CH1b)
A/D0a
D/ A0a
A/ D1a
D/A1a
A/ D0b
D/A0b
A/ D1b
D/A1b
PCM_SEL [1:0]_a
PCM_SEL [1:0]_b
PCM_SEL [1:0]_b
Linear PCM
Linear PCM
Linear PCM
Linear PCM
G .711
G .711
G.711
G.711
G.711
u-law
G.711
A-law
G.711
u-law
G.711
A-law
G.711
u-law
G.711
A-law
G.711
u-law
G.711
A-law
G.711
u-law
G.711
A-law
u-law
A-law
G.711
G.711
u-law
A-law
u-law
A-law
SYNC(8kHz)
MCK
BPF
LPF
BPF
LPF
BPF
LPF
BPF
LPF
CH0_IFSEL_a
CH1_IFSEL_a
CH1_IFSEL_a
CH0_IFSEL_b
CH1_IFSEL_b
CH1_IFSEL_b
STGAIN 1b
PDWN
STGAIN 0a
STGAIN1a
CH0_IFSEL_b
STGAIN 0b
CONT
CH0_IFSEL_a
TXDET0 a
DTMFDE
TXDET1 a
DTMFDE
TXDET0 b
DTMFDE
TXDET1 b
DTMFDE
TONE_
TD_TX
DET0 a
TONE_
TD_TX
DET1a
TONE_
TD_TX
DET0b
TONE_
TD_TX
DET1b
T0a
T1a
T0b
T1b
POWER
Sin
Rout
Sin
Rout
Sin
Rout
Sin
Rout
Echo Canceller
Echo Canceller
Echo Cbnceller
Echo Cbnceller
TONE_TXDET0_a
DTMF0_DET_a
DTMF0_C[ 3:0]_a
ANS_TXDET 0_a
ANSPM _TXDET 0_a
TONE_TXDET1_a
DTMF1_DET_a
DTMF1_C[3:0]_a
ANS_TXDET1_a
ANSPM _TXDET1_a
TONE_TXDET0_b
DTMF0_DET_b
DTMF0_C[3:0]_b
ANS_TXDET0_b
ANSPM _TXDET0_b
TONE_TXDET0_b
DTMF1_DET_b
DTMF1_C[3:0]_b
ANS_TXDET1_b
ANSPM _TXDET1_b
(CH0 a)
(CH1 a)
(CH0b)
(CH1b)
FSKGEN 0a
FSKGEN1a
Sout
FSKGEN 0b
Sout
FSKGEN 1b
Sout
Sout
Rin
Rin
Rin
Rin
FGEN 0_FLAG_a
FGEN 1_FLAG_a
FGEN0_FLAG_b
FGEN1_FLAG_b
TGEN 0_EXFLAG _a
TGEN 1_EXFLAG _a
TGEN 0_EXFLAG _b
TGEN 1_EXFLAG _b
TXGAIN 0
_CH1a
TXGAIN 0
_CH0b
RXGAIN 1
_CH0b
TXGAIN 0
TXGAIN0
_CH0a
RXGAIN1
_CH1a
RXGAIN1
_CH1b
TEST
RXGAIN1
_CH0a
_CH1b
Set T0_TXON_a
TXSIG_CH0a
TXSIG_CH1a
TXSIG _CH0b
TXSIG _CH1b
TGEN0 a
TGEN1 a
RXSIG_CH1a
TGEN0 b
TGEN1 b
RXSIG_CH1b
RXSIG _CH0a
RXSIG _CH0b
ON.
Note: Only one of FSKGEN 0b, TGEN0b, and DPGEN 0b can
be used at a time .
Note: Using the tone disabler function
TD_TXDET 0b) and tone detection function
TONE_TXDET0b) at the same time is not allowed .
Note: Only one of FSKGEN 0a, TGEN0a, and DPGEN 0a can
be used at a time .
Note: Using the tone disabler function
TD_TXDET0a) and tone detection function
TONE_TXDET0a) at the same time is not allowed .
MGENa
T1a
MGENb
T1b
T0a
T0b
Note: Only one of FSKGEN 1a, TGEN1a, and DPGEN 1a can be
used at a time .
Note: Using the tone disabler function
TD_TXDET1a) and tone detection function
TONE_TXDET1a) at the same time is not allowed .
MGEN_EXFLAG _b
MGEN_FRFLAG_b
MGEN_EXFLAG _a
MGEN_FRFLAG_a
R0a
R0b
T 0b
R1a
T1a
T0a
R1b
T1b
R1a
R1b
Note: Only one of FSKGEN 1b, TGEN1b, and DPGEN 1b can be
used at a time .
Note: Using the tone disabler function
TD_TXDET1b) and tone detection function
TONE_TXDET1b) at the same time is not allowed .
R0b
R0a
TXGAIN 1
TXGAIN 1
RXGAIN 0
TXGAIN 1
TXGAIN 1
_CH0a
RXGAIN0
RXGAIN 0
RXGAIN0
_CH1a
_CH1b
_CH0b
_CH0a
MGb
MGa
_CH1a
_CH0b
_CH1b
MGa
MGb
Set R1_TXON _a
Set R1_RXON_a
Set R1_RXON _b
RXDET1b
ON.
ON.
RXDET0a
RXDET1a
TIM_ b
RXDET0b
TIM_a
TONE_
TD_ RX
TONE_
TD_ RX
TONE_
TD_ RX
TONE_
TD_ RX
DET1 b
DET0 a
DET1 a
DET0 b
ON.
TXSC_SEL[1:0]_a
RXSC_SEL[ 1:0]_a
TXSC_SEL[1:0]_a
RXSC_SEL[ 1:0]_a
TXSC_SEL[1:0]_b
RXSC _SEL[1:0]_b
TXSC_SEL[1:0]_b
RXSC _SEL[1:0]_b
CODEC( CH0a)
CODEC( CH1a)
CODEC(CH0b)
CODEC(CH1b)
(TD_RXDET0b/
Speech
Speech
Speech
Speech
G.711
G.711
G.711
G.711
G.711
G.711
G.711
G.711
G.711
G.711
G.711
G.711
G.711
G.711
G.711
G.711
( u-law)
(A-law)
( u-law)
(A-law)
(TD_RXDET0a/
( u-law)
(A-law)
( u-law)
(A-law)
(u-law)
(A-law)
(u-law)
(A-law)
(u-law)
(A-law)
(u-law)
(A-law)
(TONE_RXDET0b/
(TD_RXDET 1a/
(TONE_RXDET0a/
Note: The following markings are used to indicate the functions whose use is
Use prohibited
(TD_RXDET1b/
ANS_RXDET1_b
TONE_RXDET 1_b
ANS_RXDET0_a
TONE_RXDET0_a
ANS_RXDET1_a
ANSPM _RXDET1_a
TONE_RXDET1_a
ANS_RXDET0_b
ANSPM _RXDET0_b
TONE_RXDET0_b
ANSPM _RXDET1_b
ANSPM_RXDET 0_a
(TONE_RXDET1a/
(TONE_RXDET1b/
prohibited and the functions for which restrictions
SCIF _SEL_a
SCIF _SEL_a
SCIF _SEL_a
SCIF _SEL_a
SCIF_SEL_b
SCIF_SEL_b
SCIF_SEL_b
SCIF_SEL_b
With restrictions
DP0_DET_a
DPDET0_D[7:0]_a
DP1_DET_a
DPDET1_D[7:0]_a
DP0_DET_b
DPDET0_D[7:0]_b
DP1_DET_b
DPDET1_D[7:0]_b
poa
poa
pob
pob
pia
pia
pib
pib
CH0a
CH1a
CH0a
CH1a
CH0b
CH1b
CH0b
CH1b
DPGEN 1a
DPGEN0b
DPGEN1b
DPDET 0b
DPDET0a
DPDET1a
DPDET1b
DPGEN 0a
GPIB0_b
GPIA0_a
GPIA1_a
GPIB0_a
GPIB1_a
GPIA0_b
GPIA1_b
GPIB1_b
(CR0a-CR47a)
(CR0b-CR47b)
FRAME/DMA
FRAME/DMA
Controller _a
CONTROL
Controller_b
RX-FIFO0b
RX-FIFO1b
TX-FIFO0 a
TX-FIFO1 a
RX-FIFO0a
RX-FIFO1a
Register_a
LOADERa
TX-FIFO0b
TX-FIFO1b
Register_b
LOADERb
CONTROL
FEDL7224-001FULL-01
Control
DOWN
SERIAL
Control
DOWN
SERIAL
FR0_CH0_a
FR0_CH1_a
FR1_a
FR0_CH0_b
FR0_CH1_b
FR1_b
are set.
[GPCR0a
GPCR7a]
[GPCR0b
GPCR7b]
GPIOa
GPIOb
INT_a
INT_b
to
to
ML7224-001TC
16 b
16b
8b
2b
4b
8b
8b
2b
4b
8b
ACK1B_ a
ACK0B_ a
FR1B _a
FR0B _a
A
WRB_a
RDB_ a
CSB_a
D[15:0]_a
A[7:0 ]_a
GPIOA[1:0]_ a
GPIOB[3:0]_ a
GPIOC[7 :0]_a
ACK 1B_b
ACK 0B_b
FR1B_ b
FR0B_ b
WRB_b
RDB_b
CSB _b
D[15:0]_b
A [7 :0]_b
GPIOA [1:0 ]_b
GPIOB [3:0 ]_b
GPIOC [7:0]_b
INTB_a
INTB_ b
SDO_a
SDI_a
SCLK_a
SDENB_a
SCNTEN
SDO _b
SDI_b
SCLK _b
SDENB _b
C
B
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