ml7084-001 Oki Semiconductor, ml7084-001 Datasheet - Page 33

• Manufacturer Part Number: ml7084-001
• Description: 4ch Voip Codec
• Manufacturer: Oki Semiconductor

This is the shift clock input/output pin for the PCM signal that is common to CH0a/CH1a/CH0b/CH1b.
When CLKSEL is “0”, it is necessary to input to this pin a clock signal synchronized with SYNC. Input a 128 kHz
This is the 8 kHz sync signal input/output pin of PCM signals that is common to CH0a/CH1a/CH0b/CH1b. When
Note: The input/output control and frequencies of the above SYNC and BLCK signals will be as shown in Table 1
to 2.048 MHz clock. When CLKSEL is “1”, this pin outputs a 2.048 MHz clock that is synchronous with SYNC.
CLKSEL is “0”, constantly input an 8 kHz clock synchronized with BCLK. Further, when CLKSEL is “1”, this pin
outputs an 8 kHz clock synchronous with BCLK. Long frame synchronization is used when the SYNC frame
contorl register (SYNC_SEL) is “0” and short frame synchronization is used when it is “1”.
PCMO_a
PCM signal output pin for CH0a/CH1a. It outputs a PCM signal in synchronization with the rise of BCLK or SYNC.
Regarding output from PCMO_a, data will be output only in the applicable time slot segment according to the
setting of the selected time slot position, and the output will be in a high impedance state in any other segments.
Note that if the PCM interface of CH0a/CH1a is not used, PCMO_a will be placed in a high impedance state.
Note:
Because the PCMO_a pin is an open drain output pin, be sure to connect a pull-up resistor externally.
Also, do not use a pull-up voltage larger than the digital power supply voltage (DVDD).
PCMI_a
PCM signal input pin for CH0a/CH1a. It is shifted by a fall of BCLK, and input from the MSB.
If the PCM interface of CH0a/CH1a is not used, fix input at either “0” or “1”.
PCMO_b
PCM signal output pin for CH0b/CH1b. It outputs a PCM signal in synchronization with the rise of BCLK or SYNC.
Regarding output from PCMO_b, data will be output only in the applicable time slot segment according to the
setting of the selected time slot position, and the output will be in a high impedance state in any other segments.
Note that if the PCM interface of CH0b/CH1b is not used, PCMO_b will be placed in a high impedance state.
Note:
Because the PCMO_b pin is an open drain output pin, be sure to connect a pull-up resistor externally.
Also, do not use a pull-up voltage larger than the digital power supply voltage (DVDD).
PCMI_b
PCM signal input pin for CH0b/CH1b. It is shifted by a fall of BCLK, and input from the MSB.
If the PCM interface of CH0b/CH1b is not used, fix input at either “0” or “1”.
BCLK
SYNC
OKI Semiconductor
below.
CLKSEL
“0”
“1”
(8 kHz)
(8 kHz)
Output
SYNC
Input
Table 1 Input/Output Control of SYNC and BCLK
(128 kHz to 2.048
(2.048 MHz )
Output
MHz )
BCLK
Input
Input a clock constantly after starting the power
supply.
Input a 128 kHz to 2.048 MHz clock.
A “L” level is output during the power down state.
Remarks
FEDL7224-001FULL-01
ML7224-001TC
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