ml7084-001 Oki Semiconductor, ml7084-001 Datasheet - Page 42

• Manufacturer Part Number: ml7084-001
• Description: 4ch Voip Codec
• Manufacturer: Oki Semiconductor

B.
OKI Semiconductor
When in the DMA mode (FRAME/DMA selection register_a (FD_SELa) = “1”)
The transmit buffer control timing during the DMA mode is shown in Figure 17. When the transmit buffer,
which stores the compressed speech data of the transmitting side (the speech compressing side), becomes full,
DMARQ0Ba goes to a “L” level from “H”, so that a DMA request is issued to the MCU. After the DMA
request is made, an acknowledge is input when DMAACK0Ba goes to the “0” state from “1”, and also, this
DMARQ0Ba will be cleared automatically (“L” → “H”) when a falling edge of the read enable signal is
accepted (RDBa = “1” → “0”). Read the data in the transmit buffer at the following timing simultaneously
with the acknowledgement input. DMARQ0Ba repeats a DMA request until either all data in the transmit
buffer have been read or the valid read period corresponding to the buffering time selected by the transmit
buffering time selection register (TXBUF_TIM_a) is complete.
The receive buffer control timing during the DMA mode is shown in Figure 18. When the receive buffer,
which stores the compressed speech data of the receiving side (the speech compressing side), becomes empty,
DMARQ1Ba goes to a “L” level from “H”, so that a DMA request is issued to the MCU. After the DMA
request is made, an acknowledge is input when DMAACK1Ba goes to the “0” state from “1”, and also, this
DMARQ1Ba will be cleared automatically (“L” → “H”) when a falling edge of the write enable signal is
accepted (WRBa = “1” → “0”). Write data into the receive buffer at the following timing simultaneously with
the acknowledgement input. DMARQ1Ba repeats a DMA request until either all data in the receive buffer
have been read or the valid read period corresponding to the buffering time selected by the receive buffering
time selection register (TXBUF_TIM_a) is complete.
Figure 17 Transmit Buffer Control Timing during DMA Mode
Figure 18 Receive Buffer Control Timing during DMA Mode
DMARQ0Ba
DMAACK0Ba
DMAACK1Ba
D15a-D0a
D15a-D0a
DMARQ1Ba
A7a-A0a
A7a-A0a
RDBa
Address = 80h (fixed)
Data amount = n words
RDBa
Address = 81h (fixed)
Data amount = n words
WRBa
WRBa
(Transmit buffer full)
(Receive buffer empty)
Address
Address
Data 0
Data 0
(Receive buffer full)
(Transmit buffer empty)
Data (n-1)
Address
Data 0
Data (n-1)
FEDL7224-001FULL-01
ML7224-001TC
42/225