ml7084-001 Oki Semiconductor, ml7084-001 Datasheet - Page 44

• Manufacturer Part Number: ml7084-001
• Description: 4ch Voip Codec
• Manufacturer: Oki Semiconductor

OKI Semiconductor
Download mode
Initial mode
*4
NO
Processing outside the LSI
Make settings for internal data memories
DSP_B side normal operation start
Make settings for control registers
Automatic processing
Yes
External setting
DSP_RESET_b (CR0b_B 7) = 0
PRAM data write processing
DRAM data write processing
OPE_ STATb (CR0b_B 0) = 1
inside the LSI
DSP_RESET_ b ( CR0b_ B7)
DLb_EN (DLCR0 b_B0) = 1
DL_ENb (DLCR0 b_B0) = 0
DL_ST0 _b (CR5b_ B4) = 0
Initialization inside the LSI
READYb (CR5 b_B7) = 1
READYb (CR5 b_B7) = 0
DL_ST[2 :1]_b = 00b?
Has timer T0b expired ?
Timer T0b start
DLb_ST0 =1 ?
NO
executed
= 1
Wait for 15 ms or more
Yes
Yes
Figure 19 DSP Firmware Write Control Flow
*3
*1: In the power-down state, the circuits are placed in a reset state except for the following blocks :
*2: For PRAM data write processing and DRAM data write processing , see Figure 20, “PRAM/DRAM Write
*3: Timer T0 is used to monitor normal termination of write error checking performed by the DSP firmware .
*4: If a write error occurs , reset the DSP of the error side by writing DSPa _ RESET (CR0a_B 7) = 1 and
tAVREF or more
OSC , VREF, PLL downloader circuit, and serial control circuit
Specify 1 second or longer as the timer value.
Control Flow ” .
DSPb_RESET (CR0b_B7 ) = 1 from the CPU side .
NO
*2
*2
*4
Download mode
Initial mode
NO
Make settings for internal data memories
Make settings for control registers
Yes
DSP_A side normal operation start
DSP_RESET_ a (CR0a_ B7) = 0
DRAM data write processing
OPE _STATa ( CR0a_ B0) = 1
PRAM data write processing
DSP_RESET_a (CR0a_B 7)
DLa_ EN (DLCR0a_B0 ) = 1
DL_ENa (DLCR0a_B0 ) = 0
Initialization inside the LSI
DL_ ST0_a (CR5 a_B4) = 0
READYa (CR5a_B7 ) = 1
READYa (CR5a_B7 ) = 0
DL_ST[2:1 ]_a = 00 b?
Has timer T0a expired?
Timer T0a start
DLa_ST0 = 1?
PDNB = 0
PDNB = 1
NO
executed
= 1
Yes
Yes
*3
tAVREF or more
NO
Wait for
15 ms or
more
Take an
interval of
250 μs or
more
*2
*2
Power-
down
released
DSP power-down state
*1
Download mode
Power -down state
FEDL7224-001FULL-01
Initial mode
Normal operation mode
ML7224-001TC
Error check of written data
is carried out by the DSP
firmware
Control register and
internal data memory
access prohibited interval
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