ml7084-001 Oki Semiconductor, ml7084-001 Datasheet - Page 28

• Manufacturer Part Number: ml7084-001
• Description: 4ch Voip Codec
• Manufacturer: Oki Semiconductor

This is the DMA acknowledge input pin for the DMARQ0B_b signal during DMA access of the transmit buffer of
Tie this pin to “1” when using this LSI in the frame mode (FD_SELb = “0”).
This is the DMA acknowledge input pin for the DMARQ1B_b signal during DMA access of the receive buffer of
Tie this pin to “1” when using this LSI in the frame mode (FD_SELb = “0”).
• FR0B_b (In frame mode (the FRAME/DMA selection register FD_SELb = “0”))
• DMARQ0B_b (In DMA mode (the FRAME/DMA selection register FD_SELb = “1”))
• FR1B_b (In frame mode (the FRAME/DMA selection register FD_SELb = “0”))
• DMARQ1B_b (In DMA mode (the FRAME/DMA selection register FD_SELb = “1”))
CH0b/CH1b and becomes valid in the DMA mode (FD_SELb = “1”).
CH0b/CH1b and becomes valid in the DMA mode (FD_SELb = “1”).
ACK0B_b
ACK1B_b
FR0B_b (DMARQ0B_b)
FR1B_b (DMARQ1B_b)
INTB_a
Interrupt request output pin for CH0a/CH1a. Since the interrupt notification function is not supported in this code,
this pin will always output “1”. Leave it open.
INTB_b
Interrupt request output pin for CH0b/CH1b. Since the interrupt notification function is not supported in this code,
this pin will always output “1”. Leave it open.
OKI Semiconductor
This is the transmit frame output pin which outputs the signal when the transmit buffer is full during frame access
at CH0b/CH1b. This pin outputs a “L” level when the transmit buffer becomes full, and maintains that “L” level
output until a specific number of words are read out from the MCU.
This is the DMA request output pin which outputs the signal when the transmit buffer is full during DMA access at
CH0b/CH1b. This output becomes “L” when the transmit buffer becomes full, and returns to the “H” level
automatically on the falling edge of the read enable signal (RDB_b = “1” → “0”) when there is an acknowledge
signal (ACK0B_b = “0”) from the MCU. This relationship is repeated until a specific number of words are read
out from the MCU.
This is the receive frame output pin which outputs the signal when the receive buffer is empty during frame access
at CH0b/CH1b. This pin outputs a “L” level when the receive buffer becomes empty, and maintains that “L” level
output until a specific number of words are written from the MCU.
This is the DMA request output pin which outputs the signal when the receive buffer is empty during DMA access
at CH0b/CH1b. This output becomes “L” when the receive buffer becomes empty, and returns to the “H” level
automatically on the falling edge of the write enable signal (WRB_b = “1” → “0”) when there is an acknowledge
signal (ACK1B_b = “0”) from the MCU. This relationship is repeated until a specific number of words are written
from the MCU.
FEDL7224-001FULL-01
ML7224-001TC
28/225