ml7084-001 Oki Semiconductor, ml7084-001 Datasheet - Page 59

• Manufacturer Part Number: ml7084-001
• Description: 4ch Voip Codec
• Manufacturer: Oki Semiconductor

• Valid write period WE_DCn (CH10& CH1)
• Receive error processing
Note:
This operational description is pertaining to the case of the 10 ms mode; in the 20 ms mode, the valid read period and
valid write period are as follows:
Valid read period RE_DCn (CH0 & CH1)
Valid write period WE_DCn (CH0& CH1)
4) 2-channel operation stop
Note:
1. Even in a frame in which 2-channel operation stop is set, a transmit data read request and receive data write
request of CH0/CH1 will be generated as usual. However, no error will be generated even if a read of transmit data
or a write of receive data of the stopped channel is not perfomred.
2. Once RXREQ_DC is cleared to “0”, it is no longer necessary to write to RXFLAG.
3. A wait time of at least 10 ms is required after TXREQ_DC = 0 and RXREQ_DC = 0 are set before starting a
5) Single-channel operation in progress
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2-channel operation again, following a stop of a channel operation.
The following describes the operation when receive data is written in the order of CH0 to CH1.
Write CH0 receive data (80 bytes) by the first receive data write request (FR1 = 1&RXREQ_First = 1).
Also, before starting to write CH0 receive data, by setting the receive data write channel notification register
(RXFLAG) to “0b”, notify this LSI that CH0 receive data will be written. Once the writing of the CH0 receive
data is finished, the second receive data write request (FR1 = 1 & RXREQ_First = 0) will be made.
Write CH1 receive data (80 bytes) by the second write request. Also in this case, before starting to write CH1
receive data, by setting the receive data write channel notification register (RXFLAG) to “1b”, notify this LSI
that CH1 receive data will be written. Note that, regardless of the first or second time, FR1 is set to “1” when a
receive data write request is made.
The valid write period will be 9 ms.
Finish writing CH0 receive data and CH1 receive data within the valid write period.
If a write from the MCU side does not finish within the valid write period, the receive error of the applicable
channel (CH0: RXERR_CH0, CH1: RXERR_CH1) will be set to “1”. The receive error will be held until
immediately before the frame during which the receive data of the applicable channel has normally been written
is terminated in the succeeding valid write periods. If an error occurs, generated data is output according to the
PLC (Packet Loss Concealment) algorithm defined in G.711 Appendix I. However, the decoder outputs silence
data if the G.711 PLC function is disabled. Also, if the receive data of the same channel is written within one
frame, the invalid-write-on-the-receive-side error (RXBW_ERR) is set to “1”. RXBW_ERR will be held until
immediately before the frame during which invalid receive data has no longer been written is terminated in the
succeeding valid write periods.
Finish reading the CH0 and CH1 transmit data within 18.0 ms after the CH0 transmit data read request
(FR0_CH0=1) is generated.
The valid write period will be 18.0 ms.
Stop the speech codec of the channel to be stopped. (This example shows a case where the speech codec of CH1
is stopped.)
This is a state in which only CH0 transmit data and receive data are exchanged.
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