ml7084-001 Oki Semiconductor, ml7084-001 Datasheet - Page 58

• Manufacturer Part Number: ml7084-001
• Description: 4ch Voip Codec
• Manufacturer: Oki Semiconductor

Operational Description
1) single-channel operation in progress
2) 2-channel operation activated
3) 2-channel operation in progress
• 2-channel transmit request status notification register (TXREQ_DC)
• Order of channels to read
• Reading procedure
• Valid read period RE_DCn(CH0 & CH1)
• Transmit error processing
• 2-channel receive request status notification register (RXREQ_DC)
• Order of channels to write
• Writing procedure
OKI Semiconductor
Transmission
Reception
Indicates a state in which only CH0 transmit data and receive data are being exchanged.
To also activate CH1 from the single-channel operation state at CH0, set SC_CH1EN=1 (and SC_CH0EN=1).
Encoder:
Starts encoding CH0 and CH1 signals a maximum of 1 frame after SC_CH1EN is set to “1”.
Decoder:
Makes two requests to write receive data in one frame a maximum of 1 frame after SC_CH1EN is set to “1”.
While a request to read transmit data is being made twice in one frame, the 2-channel transmit requesting
notification register (TXREQ_DC) is set to “1”.
Two requests to read transmit data are made in the order of CH0 and then CH1 within one frame. However, if a
read from the MCU side does not finish for a CH0 transmit data read request, a request to read CH1 transmit
data will not be generated.
Once the encoding processing for one frame of each of the CH0 and CH1 signals is finished, a CH0 transmit
data read request will be made as FR0_CH0 = 1. Read CH0 transmit data (80 bytes) by a read request. Once the
reading of the CH1 transmit data is finished, a CH1 transmit data read request will be made as FR0_CH1 = 1.
Read CH1 transmit data (80 bytes) by a read request.
Complete the CH0 and CH1 transmit data read-out within 9.0 ms after a CH0 transmit data read request is
generated (FR0_CH1=0).
If a read from the MCU side is not finished within the valid read period, the transmit error of the applicable
channel (CH0: TXERR_CH0, CH1: TXERR_CH1) will be set to “1”. The transmit error will be held until
immediately before the frame during which the transmit data of the applicable channel has normally been read
is terminated in the succeeding valid read periods. Even if a data read-out has not been finished, the data in the
transmit buffer will be updated as usual.
In this operating state, the 2-channel receive requesting notification register (RXREQ_DC) is set to “1”, and
two requests to write receive data in one frame are notified to the MCU side.
There is no specification as to the order of channles to write, so write receive data in either the order of CH0 to
CH1, or CH1 to CH0 within one frame.
Note:
Do not write the receive data of the same channel within one frame, such as CH0 to CH0, or CH1 to CH1.
In case the receive data of the same channel is written within one frame, the receive data written by the first
receive request will be decoded, but the receive data written by the second receive requst will be discarded,
setting the invalid-write-on-the-receive-side error (RXBW_ERR) to “1”.
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