ml7084-001 Oki Semiconductor, ml7084-001 Datasheet - Page 78

• Manufacturer Part Number: ml7084-001
• Description: 4ch Voip Codec
• Manufacturer: Oki Semiconductor

(0) CR0
*1:
the DSP firmware has been written.
B7 : DSP reset control register
B6 : Analog front end CH1 power down control register
B5 : Analog front end CH0 power down control register
B4–B2 : Reserved bits. Do not change the initial values.
B1 : SYNC frame control register
OKI Semiconductor
setting can be
Mode where
It is automatically set to “1” by the cancellation of hardware power down (PDNB = 0→1). Write “0” after
Initial value
0 : No reset
1 : Reset
The DSP can be placed in a reset state by setting this bit to “1” for at least 200 ns.
The contents of the control registers (excluding DLCR0–5) and internal data memories will automatically be
cleared when reset. The reset state can be canceled by setting this bit to “0” after setting it to “1”.
0 : Normally operating state
1 : Power down state (except AVREF)
The analog front end CH1 is powered down by setting this bit to “1”.
It is recommended to set this bit to “1” if the analog front end CH1 is not used.
Also, when setting this bit to “1”, set the output of VFRO1 to the AVREF side (“0”) with the VFRO1 selection
register (VFRO1_SEL).
0 : Normally operating state
1 : Power down state (except AVREF)
The analog front end CH0 is powered down by setting this bit to “1”.
It is recommended to set this bit to “1” if the analog front end CH0 will not be used.
Also, when setting this bit to “1”, set the output of VFRO0 to the AVREF side (“0”) with the VFRO0 selection
register (VFRO0_SEL).
Note:
In this code, selecting an analog interface as a front end interface is not allowed; therefore, be sure to set
AFE1_PDN = 1 and AFE0_PDN = 1 while in the initial mode.
0: Long frame synchronization signal
1: Short frame synchronization signal
Note:
The clocks of a PCM interface (SYNC and BCLK) are common on the DSP_A side and DSP_B side
Therefore, in the selection of long frame synchronization or short frame synchronization, short frame
synchoronization will be selected if “1” is set in either the SYNC frame control register (SYNC_SEL_a) on the
DSP_A side or the SYNC frame control register (SYNC_SEL_b) on the DSP_B side.
changed
CR0
RESET
DSP_
/E, D
0
B7
(*1)
AFE1_
PDN
B6
I/
0
AFE0_
PDN
B5
I/
0
B4
⎯
#
0
B3
⎯
#
0
B2
⎯
#
0
SYNC_
SEL
B1
I/
0
FEDL7224-001FULL-01
OPE_
STAT
ML7224-001TC
B0
I/
0
R/W
R/W
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