ml7084-001 Oki Semiconductor, ml7084-001 Datasheet - Page 41

• Manufacturer Part Number: ml7084-001
• Description: 4ch Voip Codec
• Manufacturer: Oki Semiconductor

A.
OKI Semiconductor
When in the Frame Mode (FRAME/DMA selection register_a (FD_SELa) = “0”)
The control timing of the transmit buffer and the method of accessing it during the frame mode are shown in
Figure 15.
When the transmit buffer, which stores the compressed speech data of the transmitting side (the speech
compressing side), becomes full, FR0Ba goes to a “L” level from “H”, so that a read request is issued to the
MCU. Read the data in the transmit buffer during the following timing. The read address of the transmit buffer
is “80h.”
Also, FR0Ba holds a “L” level until either all data in the transmit buffer have been read or the valid read period
corresponding to the buffering time selected by the transmit buffering time selection register (TXBUF_TIM_a)
is complete.
The receive buffer control timing during the frame mode is shown in Figure 16.
When the receive buffer, which stores the compressed speech data of the receiving side (the speech expanding
side), becomes empty, FR1Ba goes to a “L” level from “H”, so that a write request is issued to the MCU. Write
data into the receive buffer during the following timing. The write address of the receive buffer is “81h.”
FR1Ba holds a “L” level until either the receive buffer has been written to its full capacity or the valid write
period corresponding to the buffering time selected by the receive buffering time selection register
(RXBUF_TIM_a) is complete.
D15a-D0a
Address = 81h (fixed)
Data amount = n words
FR1Ba
A7a-A0a
RDBa
(Receive buffer empty)
D15a-D0a
CSBa
WRBa
A7a-A0a
FR0Ba
Address = 80h (fixed)
Data amount = n words
RDBa
CSBa
WRBa
(Transmit buffer full)
Figure 15 Transmit Buffer Control Timing
Figure 16 Receive Buffer Control Timing
Address
Address
Data 0
Data 0
(Transmit buffer empty)
Address
Data (n-1)
Data (n-1)
Address
(Receive buffer full)
FEDL7224-001FULL-01
ML7224-001TC
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