ml7084-001 Oki Semiconductor, ml7084-001 Datasheet - Page 30

• Manufacturer Part Number: ml7084-001
• Description: 4ch Voip Codec
• Manufacturer: Oki Semiconductor

FEDL7224-001FULL-01
OKI Semiconductor
ML7224-001TC
AIN0N_b, AIN0P_b, GSX0_b
Transmission analog input and transmission level adjustment pins for CH0b. AIN0N_b is connected to the inverting
input pin of the internal transmit amplifier, and AIN0P_b is connected to the non-inverting input pin. GSX0_b is
conneced to the output pin of the internal transmit amplifier. For more information about level adjustment, see
Figure 10.
At hardware power down (PDNB = “0”), or in a reset state on the DSP_B side (DSP_RESET_b = “1”), the output of
GSX0_b will be placed in a high impedance state. Since the use of an analog interface is prohibited in this code,
short GSX0_b and AIN0N_b, and connect AIN0P_b with AVREF.
VFRO0_b
Reception analog output pin for CH0b. VFRO0_b is connected to the output pin of the internal receive amplifier. For
the output signal of VFRO0_b, output can be selected with the VFRO0 selection register_b (VFRO0_SEL_b). When
selected (“1”), a reception signal is output; when unselected (“0”), AVREF (approximately 1.4 V) is output. At
hardware power down (PDNB = “0”), or in a reset state on the DSP_B side (DSP_RESET_b = “1”), the output of
this pin will be placed in a high impedance state. It is recommended to use the output signal via a capacitor for DC
coupling.
Because the use of an analog interface is prohibited in this code, leave this pin open.
Note:
If output selection is changed during a call, minor noise will be generated. Therefore, it is recommended to select an
output before starting a call, and then start a call after output selection. When canceling a reset or resetting, it is
recommended to do so with the output of VFRO0_b selected to the AVREF output side.
AIN1N_b, AIN1P_b, GSX1_b
Transmission analog input and transmission level adjustment pins for CH1b. AIN1N_b is connected to the inverting
input pin of the internal transmit amplifier, and AIN1P_b is connected to the non-inverting input pin. GSX1_b is
conneced to the output pin of the internal transmit amplifier. For more information about level adjustment, see
Figure 10.
At hardware power down (PDNB = “0”), or in a reset state on the DSP_B side (DSP_RESET_b = “1”), the output of
GSX1_b will be placed in a high impedance state. Since the use of an analog interface is prohibited in this code,
short GSX1_b and AIN1N_b, and connect AIN1P_b with AVREF.
VFRO1_b
Reception analog output pin for CH1b. VFRO1_b is connected to the output pin of the internal receive amplifier. For
the output signal of VFRO1_b, output can be selected with the VFRO1 selection register_b (VFRO1_SEL_b). When
selected (“1”), a reception signal is output; when unselected (“0”), AVREF (approximately 1.4 V) is output. At
hardware power down (PDNB = “0”), or in a reset state on the DSP_B side (DSP_RESET_b = “1”), the output of
this pin will be placed in a high impedance state. It is recommended to use the output signal via a capacitor for DC
coupling.
Because the use of an analog interface is prohibited in this code, leave this pin open.
Note:
If output selection is changed during a call, minor noise will be generated. Therefore, it is recommended to select an
output before starting a call, and then start a call after output selection. When canceling a reset or resetting, it is
recommended to do so with the output of VFRO1_b selected to the AVREF output side.
AVREF
This is the output pin for the analog signal ground potential. The output potential at this pin will be about 1.4 V.
Connect a 2.2 to 4.7 μF (aluminum electrolytic type) capacitor and a 0.1 μF (ceramic type) capacitor in parallel
between this pin and the GND pin as bypass capacitors. The output at the AVREF pin goes to 0.0 V in the hardware
power-down state. The voltage starts rising after the hardwdare power-down state is released (PDNB = “1”). Also,
if the output of the AVREF pin is used externally, use it via a buffer.
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