ml7084-001 Oki Semiconductor, ml7084-001 Datasheet - Page 27

• Manufacturer Part Number: ml7084-001
• Description: 4ch Voip Codec
• Manufacturer: Oki Semiconductor

This is the DMA acknowledge input pin for the DMARQ0B_a signal during DMA access of the transmit buffer of
Tie this pin to “1” when using this LSI in the frame mode (FD_SELa = “0”).
This is the DMA acknowledge input pin for the DMARQ1B_a signal during DMA access of the receive buffer of
Tie this pin to “1” when using this LSI in the frame mode (FD_SELa = “0”).
• FR0B_a (In frame mode (the FRAME/DMA selection register FD_SELa = “0”))
• DMARQ0B_a (In DMA mode (the FRAME/DMA selection register FD_SELa = “1”))
• FR1B_a (In frame mode (the FRAME/DMA selection register FD_SELa = “0”))
• DMARQ1B_a (In DMA mode (the FRAME/DMA selection register FD_SELa = “1”))
CH0a/CH1a and becomes valid in the DMA mode (FD_SELa = “1”).
CH0a/CH1a and becomes valid in the DMA mode (FD_SELa = “1”).
ACK0B_a
ACK1B_a
FR0B_a (DMARQ0B_a)
FR1B_a (DMARQ1B_a)
OKI Semiconductor
This is the transmit frame output pin which outputs the signal when the transmit buffer is full during frame access
at CH0a/CH1a. This pin outputs a “L” level when the transmit buffer becomes full, and maintains that “L” level
output until a specific number of words are read out from the MCU.
This is the DMA request output pin which outputs the signal when the transmit buffer is full during DMA access at
CH0a/CH1a. This output becomes “L” when the transmit buffer becomes full, and returns to the “H” level
automatically on the falling edge of the read enable signal (RDB_a = “1” → “0”) when there is an acknowledge
signal (ACK0B_a = “0”) from the MCU. This relationship is repeated until a specific number of words are read
out from the MCU.
This is the receive frame output pin which outputs the signal when the receive buffer is empty during frame access
at CH0a/CH1a. This pin outputs a “L” level when the receive buffer becomes empty, and maintains that “L” level
output until a specific number of words are written from the MCU.
This is the DMA request output pin which outputs the signal when the receive buffer is full during DMA access at
CH0a/CH1a. This output becomes “L” when the receive buffer becomes empty, and returns to the “H” level
automatically on the falling edge of the write enable signal (WRB_a = “1” → “0”) when there is an acknowledge
signal (ACK1B_a = “0”) from the MCU. This relationship is repeated until a specific number of words are written
from the MCU.
FEDL7224-001FULL-01
ML7224-001TC
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