am79c970 Advanced Micro Devices, am79c970 Datasheet - Page 103

• Manufacturer Part Number: am79c970
• Description: Pcnettm-pci Single-chip Ethernet Controller For Pci Local Bus
• Manufacturer: Advanced Micro Devices

CSR67: Next Transmit Status
Bit
31–16 RES
15–8
7–0
CSR72: Receive Ring Counter
Bit
31–16 RES
15–0 RCVRC
CSR74: Transmit Ring Counter
Bit
31–16 RES
15–0 XMTRC
1-970
AMD
NXST
Name
Name
Name
RES
Read/write accessible only when
STOP bit is set. These bits are
unaffected
S_RESET or STOP.
Description
Reserved locations. Written as
ZEROs and read as undefined.
Next Transmit Status. This field
is a copy of bits 31–24 of TMD1 of
the next transmit descriptor.
Read/write accessible only when
STOP bit is set. These bits are
unaffected
S_RESET or STOP.
Reserved locations. Read and
written as ZERO.
Accessible only when STOP bit is
set.
Description
Reserved locations. Written as
ZEROs and read as undefined.
Receive Ring Counter location.
Contains a Two’s complement
binary number used to number
the current receive descriptor.
This counter interprets the value
in CSR76 as pointing to the first
descriptor. A counter value of
ZERO corresponds to the last
descriptor in the ring.
Read/write accessible only when
STOP bit is set. These bits are
unaffected
S_RESET or STOP.
Description
Reserved locations. Written as
ZEROs and read as undefined.
Transmit Ring Counter location.
Contains a Two’s complement
binary number used to number
the current transmit descriptor.
This counter interprets the value
in CSR78 as pointing to the first
descriptor. A counter value of
ZERO corresponds to the last
descriptor in the ring.
Read/write accessible only when
STOP bit is set. These bits are
by
by
by
H_RESET,
H_RESET,
H_RESET,
P R E L I M I N A R Y
Am79C970
CSR76: Receive Ring Length
Bit
31–16 RES
15–0 RCVRL
CSR78: Transmit Ring Length
Bit
31–16 RES
15–0 XMTRL
CSR80: DMA Transfer Counter and FIFO Thresh-
old Control
Bit
31–16 RES
15–14 RES
Name
Name
Name
unaffected
S_RESET or STOP.
Description
Reserved locations. Written as
ZEROs and read as undefined.
Receive Ring Length. Contains
the two’s complement of the re-
ceive descriptor ring length. This
register is initialized during the
PCnet-PCI initialization routine
based on the value in the RLEN
field of the initialization block.
However, this register can be
manually altered. The actual re-
ceive ring length is defined by the
current value in this register. The
ring length can be defined as any
value from 1 to 65535.
Read/write accessible only when
STOP bit is set. These bits are
unaffected
S_RESET or STOP.
Description
Reserved locations. Written as
ZEROs and read as undefined.
Transmit Ring Length. Contains
the two’s complement of the
transmit descriptor ring length.
This register is initialized during
the PCnet-PCI initialization rou-
tine based on the value in the
TLEN field of the initialization
block. However, this register can
be manually altered. The actual
transmit ring length is defined by
the current value in this register.
The ring length can be defined as
any value from 1 to 65535.
Read/write accessible only when
STOP bit is set. These bits are
unaffected
S_RESET or STOP.
Description
Reserved locations. Written as
ZEROs and read as undefined.
Reserved locations. Read as
ones and written as ZERO.
by
by
by
H_RESET,
H_RESET,
H_RESET,