am79c970 Advanced Micro Devices, am79c970 Datasheet - Page 118

• Manufacturer Part Number: am79c970
• Description: Pcnettm-pci Single-chip Ethernet Controller For Pci Local Bus
• Manufacturer: Advanced Micro Devices

EEDET Value
(BCR19[3])
0
0
1
1
Connected?
EEPROM
Yes
Yes
PREAD command will terminate
early, the PREAD bit will be
cleared to a ZERO and the
PVALID bit will remain reset with
a value of ZERO. This applies to
the
EEPROM after H_RESET as
well as to host initiated PREAD
commands. EEPROM program-
mable locations on board the
PCnet-PCI controller will be set
to their default values by such an
aborted PREAD operation. For
example, if the aborted PREAD
operation immediately followed
the H_RESET operation, then
the final state of the EEPROM
programmable locations will be
equal to the H_RESET program-
ming for those locations.
If a PREAD command is given to
the PCnet-PCI controller and the
auto-detection pin (EESK/LED1)
indicates that no EEPROM is
present, then the EEPROM read
operation will still be attempted.
Note that at the end of the H_RE-
SET operation, a read of the
EEPROM will be performed
automatically. This H_RESET–
generated EEPROM read func-
tion will not proceed if the
No
No
automatic
EEPROM read operation is attempted.
Entire read sequence will occur,
checksum failure will result, PVALID
is reset to ZERO.
EEPROM read operation is attempted.
Entire read sequence will occur, checksum then EEPROM read operation is aborted and
operation will pass, PVALID is set to ONE. PVALID is reset to ZERO.
EEPROM read operation is attempted.
Entire read sequence will occur, checksum read sequence will occur, checksum failure
failure will result, PVALID is reset to ZERO. will result, PVALID is reset to ZERO.
EEPROM read operation is attempted.
Entire read sequence will occur, checksum Entire read sequence will occur, checksum
operation will pass, PVALID is set to ONE. operation will pass, PVALID is set to ONE.
Result if PREAD is Set to ONE
read
Table 10. EEDET Combinations
P R E L I M I N A R Y
of
the
Am79C970
13
EEDET
First TWO EESK clock cycles are
generated, then EEPROM read
operation is aborted and PVALID is
reset to ZERO.
First TWO EESK clock cycles are generated,
EEPROM read operation is attempted. Entire
EEPROM read operation is attempted.
Read Operation Following H_RESET
Result of Automatic EEPROM
auto-detection pin (EESK/LED1)
indicates that no EEPROM is
present.
PREAD is set to ZERO during
H_RESET and is unaffected by
S_RESET or the STOP bit.
PREAD is only writeable when
the STOP bit is set to ONE.
EEPROM Detect. This bit indi-
cates the sampled value of the
EESK/LED1 pin at the end of
H_RESET. This value indicates
whether or not an EEPROM is
present at the EEPROM inter-
face. If this bit is a ONE, it indi-
cates that an EEPROM is
present. If this bit is a ZERO, it in-
dicates that an EEPROM is not
present.
The value of this bit is determined
at the end of the H_RESET op-
eration. It is unaffected by S_RE-
SET or the STOP bit.
This bit is not writeable. It is read
only.
The following table indicates the
possible combinations of EEDET
and
EEPROM and the resulting op-
erations that are possible on the
EEPROM Microwire interface:
the
existence
AMD
of
1-985
an