am79c970 Advanced Micro Devices, am79c970 Datasheet - Page 67

• Manufacturer Part Number: am79c970
• Description: Pcnettm-pci Single-chip Ethernet Controller For Pci Local Bus
• Manufacturer: Advanced Micro Devices

Table 6 describes all possible bus master accesses that
the PCnet-PCI controller will perform. The right most
Note that all PCnet-PCI controller master read opera-
tions will always activate all byte enables. Therefore, no
one-, two- or three-byte read operations are indicated in
the table.
In the instance where a transmit buffer pointer address
begins on a non-DWORD boundary, the pointer will be
truncated to the next DWORD boundary address that
lies below the given pointer address and the first read
access from the transmit buffer will be indicated on the
byte enable signals as a four-byte read from this ad-
dress. Any data from byte lanes that lie outside of the
boundary indicated by the buffer pointer will be dis-
carded inside of the PCnet-PCI controller. Similarly, if
the end of a transmit buffer occurs on a non-DWORD
boundary, then all byte lanes will be indicated as active
by the byte enable signals, and any data from byte lanes
that lie outside of the boundary indicated by the buffer
pointer will be discarded inside of the PCnet-PCI
controller.
Slave Access to I/O Resources
The PCnet-PCI device is always a 32-bit peripheral on
the system bus. However, the width of individual soft-
ware resources on board the PCnet-PCI controller may
be either 16-bits or 32-bits. The PCnet-PCI controller
I/O resource widths are determined by the setting of the
DWIO bit as indicated in the following table:
1-934
* Cases marked with an asterisk represent extreme boundary conditions that are the result of programming one- and two-byte
Access
4-byte read
4-byte write
3-byte write
3-byte write
2-byte write
2-byte write
2-byte write
1-byte write
1-byte write
1-byte write
1-byte write
buffer sizes, and therefore will not be seen under normal circumstances.
AMD
Mode
Read
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Table 6. Bus Master Accesses
P R E L I M I N A R Y
Am79C970
BE[3:0]
1001*
1101*
1011*
0000
0000
1000
0001
1100
0011
1110
0111
column lists all operations that may execute the given
access:
Note that when I/O resource width is defined as 32 bits
(DWIO mode), the upper 16 bits of the I/O resource is
reserved and written as ZEROS and read as undefined,
except for the APROM locations and CSR88 . The
APROM locations and CSR88 are the only I/O re-
sources for which all 32 bits will have defined values.
However, this is true only when the PCnet-PCI controller
is in DWIO mode.
Configuring the PCnet-PCI controller for DWIO mode is
accomplished whenever there is any attempt to perform
a 32-bit write access to the RDP location (offset 10h).
See the DWIO section for more details.
DWIO Setting Resource Width
DWIO = 0
DWIO = 1
Operation
descriptor read
or initialization block read
or transmit data buffer read
descriptor write
or receive data buffer write
descriptor write
or receive data buffer write
receive data buffer write
receive data buffer write
receive data buffer write
receive data buffer write
receive data buffer write
receive data buffer write
receive data buffer write
receive data buffer write
Controller I/O
PCnet-PCI
16-bit
32-bit
Example Application
Existing PCnet-ISA
driver that assumes
16-bit I/O mapping
and 16-bit resource
widths
New drivers written
specifically for the
PCnet-PCI controller