am79c970 Advanced Micro Devices, am79c970 Datasheet - Page 127

• Manufacturer Part Number: am79c970
• Description: Pcnettm-pci Single-chip Ethernet Controller For Pci Local Bus
• Manufacturer: Advanced Micro Devices

Transmit Descriptors
When SSIZE32=0 (BCR 20, bit 8), then the software
structures are defined to be 16 bits wide, and transmit
descriptors look like this (CXDA = Current Transmit De-
scriptor Address):
When SSIZE32=1 (BCR 20, bit 8), then the software structures are defined to be 32 bits wide, and transmit descriptors
look like this (CXDA = Current Transmit Descriptor Address):
TMD0
Bit
31–0 TBADR
TMD1
Bit
31
30
1-994
CXDA+0Ch
CXDA+00h
CXDA+04h
CXDA+08h
Address
CXDA+00h
CXDA+02h
CXDA+04h
CXDA+06h
Address
AMD
Name
Name
OWN
ERR
BUFF
OWN
31
BUFF
OWN
15
1
Description
Transmit Buffer address. This
field contains the address of the
transmit buffer that is associated
with this descriptor.
Description
This bit indicates that the de-
scriptor entry is owned by the
host (OWN=0) or by the PCnet-
PCI controller (OWN=1). The
host sets the OWN bit after filling
the buffer pointed to by the de-
scriptor entry. The PCnet-PCI
controller clears the OWN bit af-
ter transmitting the contents of
the buffer. Both the PCnet-PCI
controller and the host must not
alter a descriptor entry after it has
relinquished ownership.
ERR is the OR of UFLO, LCOL,
LCAR, or RTRY. ERR is set by
UFLO
ERR
30
UFLO
ERR
14
Table 17. 16-Bit Data Structure Transmit Descriptor
Table 18. 32-Bit Data Structure Transmit Descriptor
1
ADD_/
NO_
FCS
DEF
EX
29
ADD_/
NO_
FCS
DEF
EX
13
1
MORE
LCOL
28
P R E L I M I N A R Y
MORE
LCOL
12
1
LCAR
Am79C970
ONE
27
LCAR
ONE
11
TBADR[15:0]
RTRY
29 ADD_FCS_
DEF
TBADR[31:0]
RESERVED
26
NO_FCS
ADD_FCS
RTRY
DEF
10
STP
25
ENP
TDR
STP
24
9
the PCnet-PCI controller and
cleared by the host. This bit is set
in the current descriptor when the
error occurs, and therefore may
be set in any descriptor of a
chained buffer transmission.
Bit 29 functions as ADD_FCS
when programmed for the default
I/O style of PCnet-ISA and when
programmed for the I/O style
PCnet-PCI controller. Bit 29
functions as NO_FCS when
programmed for the I/O style
ILACC.
ADD_FCS dynamically controls
the generation of FCS on a frame
by frame basis. It is valid only if
the STP bit is set. When
ADD_FCS is set, the state of
DXMTFCS is ignored and trans-
mitter FCS generation is acti-
vated. When ADD_FCS = 0, FCS
generation
DXMTFCS. ADD_FCS is set by
the host, and unchanged by the
PCnet-PCI controller. This was a
reserved bit in the LANCE
BCNT
23–16
RES
ENP
8
TDR
is
15–4
1111
RES
TBADR[23:16]
controlled
7–0
BCNT
TRC
3–0
by