am79c970 Advanced Micro Devices, am79c970 Datasheet - Page 92

• Manufacturer Part Number: am79c970
• Description: Pcnettm-pci Single-chip Ethernet Controller For Pci Local Bus
• Manufacturer: Advanced Micro Devices

4
3
2
1
RCVCCOM
TXSTRTM
TXSTRT
JAB
writing a 1 to this bit. Also cleared
by H_RESET, S_RESET or by
setting the STOP bit. Writing a 0
has no effect.
When RCVCCO is set, INTA is
asserted if IENA is ONE and the
mask bit RCVCCOM is ZERO.
When the value 01h has been
programmed into the SWSTYLE
register (BCR20, bits 7–0) for
ILACC (Am79C900) compatibil-
ity, then this bit has no meaning
and PCnet-PCI controller will
never set the value of this bit to
ONE.
Receive Collision Counter Over-
flow Mask.
If RCVCCOM is set, RCVCCO
will be unable to set INTR in
CSR0.
RCVCCOM is set by H_RESET
or S_RESET and is not affected
by STOP bit.
When the value 01h has been
programmed into the SWSTYLE
register (BCR20, bits 7–0) for
ILACC (Am79C900) compatibil-
ity, then this bit has no meaning
and PCnet-PCI controller will set
the value of this bit to ZERO.
Transmit Start status is set when-
ever PCnet-PCI controller begins
transmission of a frame.
When TXSTRT is set, INTA is as-
serted if IENA = 1 and the mask
bit TXSTRTM (CSR4 bit 2) is
clear.
TXSTRT is set by the MAC Unit
and cleared by writing a “1”, by
H_RESET, S_RESET or by as-
serting the STOP bit. Writing a
“0” has no effect.
Transmit
TXSTRTM is set, the TXSTRT bit
in CSR4 will be masked and un-
able to set INTR flag in CSR0.
Read/Write
TXSTRTM is set by H_RESET or
S_RESET and is not affected by
the STOP bit.
Jabber Error is set when the
PCnet-PCI controller Twisted-
pair MAU function exceeds an al-
lowed transmission limit. Jabber
is set by the TMAU cell and can
only be asserted in10BASE-T
mode.
Start
Mask.
accessible.
P R E L I M I N A R Y
Am79C970
If
0
CSR6: RX/TX Descriptor Table Length
Bit
31–16 RES
15–12 TLEN
11–8
JABM
RLEN
Name
When JAB is set, INTA is as-
serted if IENA = 1 and the mask
bit JABM (CSR4 bit 0) is clear.
JAB is set by the TMAU circuit
and cleared by writing a “1”. Writ-
ing a “0” has no effect. JAB is also
cleared by H_RESET, S_RESET
or by asserting the STOP bit.
When the value 01h has been
programmed into the SWSTYLE
register (BCR20, bits 7–0) for
ILACC (Am79C900) compatibil-
ity, then this bit has no meaning
and PCnet-PCI controller will
never set the value of this bit to
ONE.
Jabber Error Mask. If JABM is
set, the JAB bit in CSR4 will be
masked and unable to set INTR
flag in CSR0.
Read/Write accessible. JABM is
set by H_RESET or S_RESET
and is not affected by the STOP
bit.
When the value 01h has been
programmed into the SWSTYLE
register (BCR20, bits 7–0) for
ILACC (Am79C900) compatibil-
ity, then this bit has no meaning
and PCnet-PCI controller will set
the value of this bit to ZERO.
Description
Reserved locations. Written as
ZEROs and read as undefined.
Contains a copy of the transmit
encoded ring length (TLEN) field
read from the initialization block
during PCnet-PCI controller in-
itialization. This field is written
during the PCnet-PCI controller
initialization routine.
Read accessible only when
STOP bit is set. Write operations
have no effect and should not be
performed. TLEN is only defined
after initialization. These bits are
unaffected
S_RESET or STOP.
Contains a copy of the receive
encoded ring length (RLEN) read
from the initialization block dur-
ing PCnet-PCI controller initiali-
zation. This field is written during
by
H_RESET,
AMD
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