am79c970 Advanced Micro Devices, am79c970 Datasheet - Page 96

• Manufacturer Part Number: am79c970
• Description: Pcnettm-pci Single-chip Ethernet Controller For Pci Local Bus
• Manufacturer: Advanced Micro Devices

0
CSR16: Initialization Block Address Lower
Bit
31–16 RES
15–0 IADR[15:0]
CSR17: Initialization Block Address Upper
Bit
31–16 RES
15–0IADR[31:16]
CSR18: Current Receive Buffer Address Lower
Bit
31–16 RES
15–0 CRBAL
CSR19: Current Receive Buffer Address Upper
Bit
31–16 RES
15–0 CRBAU
Name
Name
Name
Name
DRX
and therefore no transmissions
are attempted. DTX = “0”, will set
TXON bit (CSR0 bit 4) if STRT
(CSR0 bit 1) is asserted.
Read/write accessible only when
STOP bit is set.
Disable
PCnet-PCI controller not access-
ing the Receive Descriptor Ring
and therefore all receive frame
data are ignored. DRX = “0”, will
set RXON bit (CSR0 bit 5) if
STRT (CSR0 bit 1) is asserted.
Read/write accessible only when
STOP bit is set.
Description
Reserved locations. Written as
ZEROs and read as undefined.
This register is an alias of CSR1.
Description
Reserved locations. Written as
ZEROs and read as undefined.
This register is an alias of CSR2.
Description
Reserved locations. Written as
ZEROs and read as undefined.
Contains the lower 16 bits of the
current receive buffer address at
which the PCnet-PCI controller
will store incoming frame data.
Read/write accessible only when
STOP bit is set. These bits are
unaffected
S_RESET or STOP.
Description
Reserved locations. Written as
ZEROs and read as undefined.
Contains the upper 16 bits of the
current receive buffer address at
which the PCnet-PCI controller
will store incoming frame data.
Read/write accessible only when
STOP bit is set. These bits are
Receiver
by
H_RESET,
results
P R E L I M I N A R Y
Am79C970
in
CSR20: Current Transmit Buffer Address Lower
Bit
31–16 RES
15–0 CXBAL
CSR21: Current Transmit Buffer Address Upper
Bit
31–16 RES
15–0 CXBAU
CSR22: Next Receive Buffer Address Lower
Bit
31–16 RES
15–0 NRBAL
CSR23: Next Receive Buffer Address Upper
Bit
31–16 RES
15–0 NRBAU
Name
Name
Name
Name
unaffected
S_RESET or STOP.
Description
Reserved locations. Written as
ZEROs and read as undefined.
Contains the lower 16 bits of the
current transmit buffer address
from which the PCnet-PCI con-
troller is transmitting.
Read/write accessible only when
STOP bit is set. These bits are
unaffected
S_RESET or STOP.
Description
Reserved locations. Written as
ZEROs and read as undefined.
Contains the upper 16 bits of the
current transmit buffer address
from which the PCnet-PCI con-
troller is transmitting.
Read/write accessible only when
STOP bit is set. These bits are
unaffected
S_RESET or STOP.
Description
Reserved locations. Written as
ZEROs and read as undefined.
Contains the lower 16 bits of the
next receive buffer address to
which the PCnet-PCI controller
will store incoming frame data.
Read/write accessible only when
STOP bit is set. These bits are
unaffected
S_RESET or STOP.
Description
Reserved locations. Written as
ZEROs and read as undefined.
Contains the upper 16 bits of the
next receive buffer address to
which the PCnet-PCI controller
will store incoming frame data.
by
by
by
by
H_RESET,
H_RESET,
H_RESET,
H_RESET,
AMD
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