am79c970 Advanced Micro Devices, am79c970 Datasheet - Page 47

• Manufacturer Part Number: am79c970
• Description: Pcnettm-pci Single-chip Ethernet Controller For Pci Local Bus
• Manufacturer: Advanced Micro Devices

entry. A device may, however, read from a descriptor
that it does not currently own. Software should always
read descriptor entries in sequential order. When soft-
ware finds that the current descriptor is owned by the
PCnet-PCI controller, then the software must not read
“ahead” to the next descriptor. The software should wait
at the unOWNed descriptor until ownership has been
granted to the software (when SPRINTEN = 1 (CSR3,
bit 5), then this rule is modified. See the SPRINTEN de-
scription). Strict adherence to these rules insures that
“Deadly Embrace” conditions are avoided.
Descriptor Ring Access Mechanism
At initialization, the PCnet-PCI controller reads the base
address of both the transmit and receive descriptor rings
into CSRs for use by the PCnet-PCI controller during
subsequent operations.
1-914
RES
AMD
RLEN
TLEN
CSR2
IADR[23:16]
Initialization
24-Bit Base Address
RES
RES
LADRF[15:0]
LADRF[31:16]
LADRF[47:32]
LADRF[63:48]
RDRA[15:0]
TDRA[15:0]
PADR[15:0]
PADR[31:16]
PADR[47:32]
Initialization Block
Block
MODE
Figure 22. 16-Bit Data Structures: Initialization Block and Descriptor Rings
Pointer to
RDRA[23:16]
TDRA[23:16]
IADR[15:0]
CSR1
P R E L I M I N A R Y
Buffers
Buffers
Xmt
Rcv
Am79C970
1st desc.
start
As the final step in the self-initialization process, the
base address of each ring is loaded into each of the cur-
rent descriptor address registers and the address of the
next descriptor entry in the transmit and receive rings is
computed and loaded into each of the next descriptor
address registers.
When SSIZE32 = 0, software data structures are 16 bits
wide. The following diagram, Figure 22, illustrates the
relationship between the Initialization Base Address,
the Initialization Block, the Receive and Transmit De-
scriptor Ring Base Addresses, the Receive and Trans-
mit Descriptors and the Receive and Transmit Data
Buffers, for the case of SSIZE32 = 0.
RMD0
1st desc.
start
TMD0
RX DESCRIPTOR RINGS
RX DESCRIPTOR RINGS
Buffer
Buffer
Data
Data
1
1
RMD1 RMD2
N
TMD1 TMD2
Rcv Descriptor
Xmt Descriptor
M
Ring
Ring
Buffer
Buffer
N
Data
Data
2
2
M
RMD3
TMD3
N
M
2nd desc.
start
2nd desc.
start
RMD0
N
TMD0
M
•
Buffer
Buffer
Data
Data
•
•
N
M
•
•
•
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