am79c970 Advanced Micro Devices, am79c970 Datasheet - Page 57

no-image

am79c970

Manufacturer Part Number
am79c970
Description
Pcnettm-pci Single-chip Ethernet Controller For Pci Local Bus
Manufacturer
Advanced Micro Devices
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
am79c970ACK
Manufacturer:
AMD
Quantity:
271
Part Number:
am79c970AKC
Manufacturer:
AMtek
Quantity:
11
Part Number:
am79c970AKC
Manufacturer:
AMD
Quantity:
20 000
Part Number:
am79c970AKC/W
Manufacturer:
AMD
Quantity:
226
Part Number:
am79c970AKC/W
Manufacturer:
AMD
Quantity:
20 000
Part Number:
am79c970AKCW
Manufacturer:
AMD
Quantity:
6 557
Part Number:
am79c970AVC
Manufacturer:
AMD
Quantity:
60
Part Number:
am79c970AVC
Manufacturer:
ST
0
Part Number:
am79c970AVC
Manufacturer:
AMD
Quantity:
20 000
Part Number:
am79c970KC
Manufacturer:
AMD
Quantity:
263
difference between BCC and phase-locked clock.
Hence, input data jitter is reduced in ISRDCLK by
10 to 1.
Carrier Tracking and End of Message
The carrier detection circuit monitors the DI inputs after
IRXCRS is asserted for an end of message. IRXCRS
de-asserts 1 to 2 bit times after the last positive transi-
tion on the incoming message. This initiates the end of
reception cycle. The time delay from the last rising edge
of the message to IRXCRS de-assert allows the last bit
to be strobed by ISRDCLK and transferred to the con-
troller section, but prevents any extra bit(s) at the end
of message.
Data Decoding
The data receiver is a comparator with clocked output to
minimize noise sensitivity to the DI inputs. Input error is
less than 35 mV to minimize sensitivity to input rise and
1-924
AMD
PCnet-PCI
DI+
DI-
Figure 25. Differential Input Termination
40.2
P R E L I M I N A R Y
Am79C970
0.01 F
fall time. ISRDCLK strobes the data receiver output at
1/4 bit time to determine the value of the Manchester bit,
and clocks the data out on IRXDAT on the following
ISRDCLK. The data receiver also generates the signal
used for phase detector comparison to the internal
MENDEC voltage controlled oscillator (VCO).
Differential Input Terminations
The differential input for the Manchester data (DI ) is
externally terminated by two 40.2
one optional common-mode bypass capacitor, as
shown in the Differential Input Termination diagram be-
low. The differential input impedance, ZIDF, and the com-
mon-mode input impedance, ZICM, are specified so that
the Ethernet specification for cable termination imped-
ance is met using standard 1% resistor terminators. If
SIP devices are used, 39
CI differential inputs are terminated in exactly the same
way as the DI pair.
0.1 F
to
40.2
AUI Isolation
Transformer
18220C-27
is also a suitable value. The
1% resistors and

Related parts for am79c970