am79c970 Advanced Micro Devices, am79c970 Datasheet - Page 94

• Manufacturer Part Number: am79c970
• Description: Pcnettm-pci Single-chip Ethernet Controller For Pci Local Bus
• Manufacturer: Advanced Micro Devices

CSR14: Physical Address Register, PADR[47:32]
Bit
31–16 RES
15–0 PADR[47:32]
CSR15: Mode Register
Bit
31–16 RES
15
14
13
DRCVBC
DRCVPA
PROM
Name
Name
Description
Reserved locations. Written as
ZEROs and read as undefined.
Physical
PADR[47:32]. The content of this
register is undefined until loaded
from the initialization block after
the INIT bit in CSR0 has been set
or a direct I/O write has been per-
formed on this register.
Read/write accessible only when
STOP bit is set. These bits are
unaffected
S_RESET or STOP.
Description
This register’s fields are loaded
during the PCnet-PCI controller
initialization routine with the cor-
responding Initialization Block
values or a direct I/O write has
been performed on this register.
Reserved locations. Written as
ZEROs and read as undefined.
Promiscuous Mode.
When PROM = “1”, all incoming
receive frames are accepted.
Read/write accessible only when
STOP bit is set.
Disable
When set, disables the PCnet-
PCI controller from receiving
broadcast messages. Used for
protocols that do not support
broadcast addressing, except as
a function of multicast. DRCVBC
is cleared by activation of H_RE-
SET or S_RESET (broadcast
messages will be received) and
is unaffected by STOP.
Read/write accessible only when
STOP bit is set.
Disable Receive Physical Ad-
dress. When set, the physical ad-
dress detection (Station or node
ID) of the PCnet-PCI controller
will
addressed to the nodes individ-
ual physical address will not be
recognized.
Read/write accessible only when
STOP bit is set.
be
Receive
Address
disabled.
by
H_RESET,
Broadcast.
Register,
P R E L I M I N A R Y
Frames
Am79C970
12
11
10
9
MENDECL
DLNKTST
DAPC
TSEL
TSEL
LRT
LRT
Disable
DLNKTST = “1”, monitoring of
Link Pulses is disabled. When
DLNKTST = “0”, monitoring of
Link Pulses is enabled. This pin
only has meaning when the
10BASE-T network interface is
selected.
Read/write accessible only when
STOP bit is set.
Disable Automatic Polarity Cor-
rection. When DAPC = “1”, the
10BASE-T receive polarity rever-
sal algorithm is disabled. Like-
wise, when DAPC = “0”, the
polarity reversal algorithm is
enabled.
This bit only has meaning when
the 10BASE-T network interface
is selected.
Read/write accessible only when
STOP bit is set.
MENDEC Loopback Mode. See
the description of the LOOP bit in
CSR15.
Read/write accessible only when
STOP bit is set.
Low Receive Threshold (T-MAU
Mode only)
Transmit Mode Select (AUI
Mode only)
Low Receive Threshold. When
LRT = “1”, the internal twisted
pair receive thresholds are re-
duced by 4.5 dB below the stan-
dard
(approximately 3/5) and the un-
squelch threshold for the RXD
circuit will be 180 mV – 312 mV
peak.
When LRT = “0”, the unsquelch
threshold for the RXD circuit will
be
value, 300 – 520 mV peak.
In either case, the RXD circuit
post squelch threshold will be
one
threshold.
This bit only has meaning when
the 10BASE-T network interface
is selected.
Read/write accessible only when
STOP bit is set. Cleared by
H_RESET or S_RESET and is
unaffected by STOP.
Transmit Mode Select. TSEL
controls the levels at which the
the
half
Link
10BASE-T
standard
of
the
Status.
10BASE-T
unsquelch
AMD
1-961
When
value