am79c970 Advanced Micro Devices, am79c970 Datasheet - Page 108

• Manufacturer Part Number: am79c970
• Description: Pcnettm-pci Single-chip Ethernet Controller For Pci Local Bus
• Manufacturer: Advanced Micro Devices

CSR114: Receive Collision Count
Bit
31–16 RES
15–0
CSR122: Receive Frame Alignment Control
Bit
31–16 RES
15–1
0
RCVALGN
Name
Name
RCC
RES
This register is always readable
and is cleared by H_RESET or
S_RESET or STOP.
A write to this register performs
an increment when the ENTST
bit in CSR4 is set.
Description
Reserved locations. Written as
ZEROs and read as undefined.
Receive Collision Count. Indi-
cates the total number of colli-
sions
receiver since the last reset of the
counter.
RCC will roll over to a count of
ZERO from the value 65535.
The RCVCCO bit of CSR4 (bit 5)
will be set each time that this
occurs.
The RCC value is read accessi-
ble at all times, regardless of the
value of the STOP bit. Write op-
erations are ignored.
cleared
S_RESET or by setting the
STOP bit.
A write to this register performs
an increment when the ENTST
bit in CSR4 is set.
Description
Reserved locations. Written as
ZEROs and read as undefined.
Reserved locations, written as
ZEROs and read as undefined.
Receive Packet Align. When set,
this bit forces the data field of ISO
8802-3 (IEEE/ANSI 802.3) pack-
ets to align to 0 MOD 4 address
boundaries (i.e. DWORD (dou-
ble-word) aligned addresses). It
is important to note that this fea-
ture will only function correctly if
all receive buffer boundaries are
DWORD aligned and all receive
buffers have 0 MOD 4 lengths. In
order to accomplish the data
alignment, the PCnet-PCI con-
troller simply inserts two bytes of
encountered
by
H_RESET
by
P R E L I M I N A R Y
RCC is
the
Am79C970
or
CSR124: Test Register 1
Bit
31–4
3
2–0
Name
RES
RPA
RES
random data at the beginning of
the receive packet (i.e. before the
ISO 8802-3 (IEEE/ANSI 802.3)
destination address field). The
MCNT field reported to the re-
ceive descriptor will not include
the extra two bytes.
RCVALGN is cleared by H_RE-
SET or S_RESET and is not af-
fected by STOP.
Read/write accessible only when
STOP bit is set.
Description
This register is used to place the
PCnet-PCI into various test
modes. Only the Runt Packet Ac-
cept is an user accessible test
mode. All other test modes are
for AMD internal use only.
ENTST must set before pro-
gramming
must be reset after writing to
CSR124 before writing to any
other register.
All bits in this register are cleared
by H_RESET or S_RESET and
are not affected by STOP.
Reserved locations. Written as
ZEROs and read as undefined.
Runt Packet Accept. This bit
forces the PCnet-PCI controller
receive logic to accept runt pack-
ets (packets shorter than 64
bytes). The state of the RPA bit
can be changed only when the
device is in the test mode (when
ENTST bit in CSR4 is set to
ONE).
To enable RPA, the user must
first write a ONE to the ENTST
bit. Next, the user must first write
a ONE to the RPA bit (CSR124,
bit 3). Finally, the user must write
a ZERO to the ENTST bit to take
the device out of test mode op-
eration. Once, the RPA bit has
been set to ONE, the device will
remain in the Runt Packet Accept
mode until the RPA bit is cleared
to ZERO.
Reserved locations. Written as
ZEROs and read as undefined.
CSR124.
AMD
ENTST
1-975