am79c970 Advanced Micro Devices, am79c970 Datasheet - Page 97

• Manufacturer Part Number: am79c970
• Description: Pcnettm-pci Single-chip Ethernet Controller For Pci Local Bus
• Manufacturer: Advanced Micro Devices

CSR24: Base Address of Receive Ring Lower
Bit
31–16 RES
15–0 BADRL
CSR25: Base Address of Receive Ring Upper
Bit
31–16 RES
15–0 BADRU
CSR26: Next Receive Descriptor Address Lower
Bit
31–16 RES
15–0 NRDAL
CSR27: Next Receive Descriptor Address Upper
Bit
31–16 RES
15–0 NRDAU
1-964
AMD
Name
Name
Name
Name
Read/write accessible only when
STOP bit is set. These bits are
unaffected
S_RESET or STOP.
Description
Reserved locations. Written as
ZEROs and read as undefined.
Contains the lower 16 bits of the
base address of the Receive
Ring.
Read/write accessible only when
STOP bit is set. These bits are
unaffected
S_RESET or STOP.
Description
Reserved locations. Written as
ZEROs and read as undefined.
Contains the upper 16 bits of the
base address of the Receive
Ring.
Read/write accessible only when
STOP bit is set. These bits are
unaffected
S_RESET or STOP.
Description
Reserved locations. Written as
ZEROs and read as undefined.
Contains the lower 16 bits of the
next RDRE address pointer.
Read/write accessible only when
STOP bit is set. These bits are
unaffected
S_RESET or STOP.
Description
Reserved locations. Written as
ZEROs and read as undefined.
Contains the upper 16 bits of the
next RDRE address pointer.
Read/write accessible only when
STOP bit is set. These bits are
unaffected
S_RESET or STOP.
by
by
by
by
by
H_RESET,
H_RESET,
H_RESET,
H_RESET,
H_RESET,
P R E L I M I N A R Y
Am79C970
CSR28: Current Receive Descriptor
Address Lower
Bit
31–16 RES
15–0 CRDAL
CSR29: Current Receive Descriptor
Address Upper
Bit
31–16 RES
15–0 CRDAU
CSR30: Base Address of Transmit Ring Lower
Bit
31–16 RES
15–0 BADXL
CSR31: Base Address of Transmit Ring Upper
Bit
31–16 RES
15–0 BADXU
Name
Name
Name
Name
Description
Reserved locations. Written as
ZEROs and read as undefined.
Contains the lower 16 bits of the
current RDRE address pointer.
Read/write accessible only when
STOP bit is set. These bits are
unaffected
S_RESET or STOP.
Description
Reserved locations. Written as
ZEROs and read as undefined.
Contains the upper 16 bits of the
current RDRE address pointer.
Read/write accessible only when
STOP bit is set. These bits are
unaffected
S_RESET or STOP.
Description
Reserved locations. Written as
ZEROs and read as undefined.
Contains the lower 16 bits of the
base address of the Transmit
Ring.
Read/write accessible only when
STOP bit is set. These bits are
unaffected
S_RESET or STOP.
Description
Reserved locations. Written as
ZEROs and read as undefined.
Contains the upper 16 bits of the
base address of the Transmit
Ring.
Read/write accessible only when
STOP bit is set. These bits are
unaffected
S_RESET or STOP.
by
by
by
by
H_RESET,
H_RESET,
H_RESET,
H_RESET,