am79c970 Advanced Micro Devices, am79c970 Datasheet - Page 66

• Manufacturer Part Number: am79c970
• Description: Pcnettm-pci Single-chip Ethernet Controller For Pci Local Bus
• Manufacturer: Advanced Micro Devices

the upper two bytes of the data bus will be undefined
since the byte mask will not be active for those bytes.
If DWIO mode has been invoked, then the BDP has a
width of 32 bits, hence, all BCR locations have 32 bits of
width and the upper two bytes of the data bus will be ac-
tive, as indicated by the byte mask. In this case, note
that the upper 16 bits of all BCR locations are reserved
and written as ZEROs and read as undefined. There-
fore, during BDP write operations in DWIO mode, the
upper 16 bits of all BCR locations should be written as
ZEROs.
RESET Register (S_RESET)
A read of the reset register creates an internal S_RE-
SET pulse in the PCnet-PCI controller. This read access
cycle must be 16 bits wide in WIO mode and 32 bits wide
in DWIO mode. The internal S_RESET pulse that is
generated by this access is different from both the as-
sertion of the hardware RST pin (H_RESET) and from
the assertion of the software STOP bit. Specifically, the
reset registers S_RESET will be the equivalent of the
assertion of the RST pin (H_RESET) assertion for all
CSR locations, but S_RESET will have no effect at all on
the BCR or PCI configuration space locations, and
S_RESET will not cause a deassertion of the REQ pin.
The NE2100 LANCE based family of Ethernet cards re-
quires that a write access to the reset register follows
each read access to the reset register. The PCnet-PCI
controller does not have a similar requirement. The write
access is not required but it does not have any
harmful effects.
Write accesses to the reset register will have no effect
on the PCnet-PCI controller.
Note that a read access of the reset register will take
longer than the normal I/O access time of the PCnet-PCI
controller. This is because an internal S_RESET pulse
will be generated due to this access, and the access will
not be allowed to complete on the system bus until the
internal S_RESET operation has been completed. This
is to avoid the problem of allowing a new I/O access to
proceed while the S_RESET operation has not yet com-
pleted, which would result in erroneous data being re-
turned by (or written into) the PCnet-PCI controller. The
length of a read of the Reset register can be as long as
64 clock cycles.
Note that a read of the reset register will not cause a
deassertion of the REQ signal, if it happens to be active
at the time of the read of the reset register. The REQ sig-
nal will remain active until the GNT signal is asserted.
Following the read of the reset register, on the next clock
cycle after the GNT signal is asserted, the PCnet-PCI
controller will deassert the REQ signal. No bus master
accesses will have been performed during this brief bus
ownership period.
P R E L I M I N A R Y
Am79C970
Note that this behavior differs from that which occurs fol-
lowing the assertion of a minimum-width pulse on the
RST pin (H_RESET). A RST pin assertion will cause the
REQ signal to deassert within six clock cycles following
the assertion. In the RST pin case, the PCnet-PCI con-
troller will not wait for the assertion of the GNT signal be-
fore deasserting the REQ signal.
Vendor Specific Word
This I/O offset is reserved for use by the system de-
signer. The PCnet-PCI controller will not respond to ac-
cesses directed toward this offset. The Vendor Specific
Word is only available when the PCnet-PCI controller is
programmed to word I/O mode (DWIO = 0).
If more than one Vendor Specific Word is needed, it is
suggested that the VSW location should be divided into
a VSW Register Address Pointer (VSWRAP) at one lo-
cation (e.g. VSWRAP at byte location 18h or word loca-
tion 30h, depending upon DWIO state) and a VSW Data
Port (VSWDP) at the other location (e.g. VSWDP at byte
location 19h or word location 32h, depending upon
DWIO state). Alternatively, the system may capture
RAP data accesses in parallel with the PCnet-PCI con-
troller and therefore share the PCnet-PCI controller
RAP to allow expanded VSW space. PCnet-PCI control-
ler will not respond to access to the VSW I/O address.
Reserved I/O Space
These locations are reserved for future use by AMD.
The PCnet-PCI controller does not respond to accesses
directed toward these locations, but future AMD prod-
ucts that are intended to be upward compatible with the
PCnet-PCI controller device may decode accesses to
these locations. Therefore, the system designer may
not utilize these I/O locations.
Hardware Access
PCnet-PCI Controller Master Accesses
The PCnet-PCI controller has a bus interface compat-
ible with PCI specification revision 2.0.
Complete descriptions of the signals involved in bus
master transactions for each mode may be found in the
pin description section of this document. Timing dia-
grams for master accesses may be found in the block
description section for the Bus Interface Unit. This sec-
tion simply lists the types of master accesses that will be
performed by the PCnet-PCI controller with respect to
data size and address information.
The PCnet-PCI controller will support master accesses
only to 32-bit peripherals. The PCnet-PCI controller
does not support master accesses to 8-bit or 16-bit
memory. The PCnet-PCI controller is not compatible
with 8-bit systems, since there is no mode that supports
PCnet-PCI controller accesses to 8-bit peripherals.
AMD
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