am79c970 Advanced Micro Devices, am79c970 Datasheet - Page 122

• Manufacturer Part Number: am79c970
• Description: Pcnettm-pci Single-chip Ethernet Controller For Pci Local Bus
• Manufacturer: Advanced Micro Devices

Initialization Block
When SSIZE32=0 (BCR20, bit 8), then the software
structures are defined to be 16 bits wide. The base ad-
dress of the Initialization block in this mode must be
aligned to a WORD boundary, i.e. CSR1, bit 0 and
CSR16, bit 0 must be set to ZERO. When SSIZE32 = 0,
the initialization block looks like Table 13.
Note that the PCnet-PCI device performs DWORD ac-
cesses to read the initialization block. This statement is
always true, regardless of the setting of the SSIZE32 bit.
RLEN and TLEN
When SSIZE32=0 (BCR20, bit 8), then the software
structures are defined to be 16 bits wide, and the RLEN
and TLEN fields in the initialization block are 3 bits wide,
occupying bits 15, 14, and 13, and the value in these
fields determines the number of Receive and Transmit
Descriptor Ring Entries (DRE) which are used in the de-
scriptor rings. Their meaning is as follows:
IADR+0Ch
IADR+00h
IADR+04h
IADR+08h
IADR+10h
IADR+14h
IADR+18h
Address
IADR+0Ch
IADR+00h
IADR+02h
IADR+04h
IADR+06h
IADR+08h
IADR+0Ah
IADR+0Eh
IADR+10h
IADR+12h
IADR+14h
IADR+16h
Address
31–28
TLEN
Bits
Bits 15–13
RLEN
TLEN
27–24
RES
Bits
Table 13. 16-Bit Data Structure Initialization Block
Table 14. 32-Bit Data Structure Initialization Block
RES
Bit 12
23–20
RLEN
Bits
0
0
P R E L I M I N A R Y
Am79C970
19–16
LADRF 15–00
LADRF 31–16
LADRF 47–32
LADRF 63–48
MODE 15–00
RES
RDRA 15–00
PADR 15–00
PADR 31–16
PADR 47–32
TDRA 15–00
Bits
Bits 11–8
PADR 31–00
RDRA 31–00
LADR 31–00
LADR 63–32
TDRA 31–00
RES
RES
When SSIZE32=1 (BCR20, bit 8), then the software
structures are defined to be 32 bits wide. The base ad-
dress of the Initialization block in this mode must be
aligned to a DOUBLE WORD boundary, i.e., CSR1, bits
0 and 1 and CSR16, bits 0 and 1 must be set to ZERO.
When SSIZE32 = 1, the initialization block looks like
Table 14.
15–12
Bits
R/TLEN
000
001
010
011
100
101
110
111
Bits 7–4
11–8
Bits
PADR 47–32
RDRA 23–16
TDRA 23–16
MODE
Bits
7–4
# of DREs
Bits 3–0
128
16
32
64
1
2
4
8
AMD
Bits
3–0
1-989