am79c970 Advanced Micro Devices, am79c970 Datasheet - Page 124

• Manufacturer Part Number: am79c970
• Description: Pcnettm-pci Single-chip Ethernet Controller For Pci Local Bus
• Manufacturer: Advanced Micro Devices

The Logical Address Filter is used in multicast address-
ing schemes. The acceptance of the incoming frame
based on the filter value indicates that the message may
be intended for the node. It is the node’s responsibility to
determine if the message is actually intended for the
node by comparing the destination address of the stored
message with a list of acceptable logical addresses.
If the Logical Address Filter is loaded with all ZEROs
and promiscuous mode is disabled, all incoming logical
addresses except broadcast will be rejected.
The Broadcast address, which is all ones, does not go
through the Logical Address Filter and is handled as
follows:
If external loopback is used, the FCS logic must be allo-
cated to the receiver (by setting the DXMTFCS bit in
CSR15, and clearing the ADD_FCS bit in TMD1) when
using multicast addressing.
When SSIZE32=1 (BCR 20, bit 8), then the software
structures are defined to be 32 bits wide, and receive de-
scriptors look like this (CRDA = Current Receive
Descriptor Address):
CRDA+0Ch
CRDA+00h
CRDA+04h
CRDA+08h
Address
If the Disable Broadcast Bit is cleared, the broadcast
address is accepted.
If the Disable Broadcast Bit is set and promiscuous
mode is enabled, the broadcast address is accepted.
If the Disable Broadcast Bit is set and promiscuous
mode is disabled, the broadcast address is rejected.
CRDA+00h
CRDA+02h
CRDA+04h
CRDA+06h
Address
OWN
31
OWN
15
1
0
ERR
30
ERR
14
1
0
Table 15. 16-Bit Data Structure Receive Descriptor
Table 16. 32-Bit Data Structure Receive Descriptor
FRAM
29
FRAM
13
1
0
OFLO
28
P R E L I M I N A R Y
OFLO
RCC
12
1
0
Am79C970
CRC
27
RESERVED
CRC
11
RBADR[15:0]
PADR
This 48-bit value represents the unique node address
assigned by the ISO 8802-3 (IEEE/ANSI 802.3) and
used for internal address comparison. PADR[0] is com-
pared with the first bit in the destination address set the
incoming frame (as received from the wire) the first ad-
dress bit transmitted on the wire, and must be ZERO.
The six hex-digit nomenclature used by the ISO 8802-3
(IEEE/ANSI 802.3) maps to the PCnet-PCI PADR regis-
ter as follows: the first byte is PADR[7:0], with PADR[0]
being the least significant bit of the byte. The second
ISO 8802-3 (IEEE/ANSI 802.3) byte is compared with
PADR[15:8], again from LS bit to MS bit, and so on. The
sixth byte is compared with PADR[47:40], the LS bit be-
ing PADR[40].
MODE
The mode register in the initialization block is copied into
CSR15 and interpreted according to the description of
CSR15.
Receive Descriptors
When SSIZE32=0 (BCR20, bit 8), then the software
structures are defined to be 16 bits wide, and receive de-
scriptors look like this (CRDA = Current Receive De-
scriptor Address):
BUFF
RBADR[31:0]
26
BUFF
10
STP
25
ENP
STP
24
9
MCNT
BCNT
23–16
RPC
RES
ENP
8
15–12
1111
0000
RBADR[23:16]
AMD
7–0
MCNT
BCNT
11–0
1-991