am79c970 Advanced Micro Devices, am79c970 Datasheet - Page 76

• Manufacturer Part Number: am79c970
• Description: Pcnettm-pci Single-chip Ethernet Controller For Pci Local Bus
• Manufacturer: Advanced Micro Devices

For each LED register, each of the status signals is
ANDed with its enable signal, and these signals are all
ORed together to form a combined status signal. Each
LED pins combined status signal runs to a pulse
stretcher, which consists of a 3-bit shift register clocked
at 38 Hz (26 ms). The data input of each shift register is
normally at logic 0. The OR gate output for each LED
register asynchronously sets all three bits of its shift reg-
ister when the output becomes asserted. The inverted
output of each shift register is used to control an LED
pin. Thus the pulse stretcher provides 2–3 clocks of
stretched LED output, or 52 ms to 78 ms.
The diagram above shows the LED signal circuit that ex-
ists for each LED pin within the PCnet-PCI controller.
H_RESET, S_RESET, and STOP
There are three different types of RESET operations
that may be performed on the PCnet-PCI device, H_RE-
SET, S_RESET and STOP. These names have been
used throughout the document. The following is a de-
scription of each type of RESET operation:
H_RESET
H_RESET= HARDWARE_RESET is a PCnet-PCI RE-
SET operation that has been created by the proper as-
sertion of the RST PIN of the PCnet-PCI device. When
the minimum pulse width timing as specified in the RST
pin description has been satisfied, then an internal RE-
SET operation will be performed.
JAB
JAB E
COL
COL E
RCVM
RCVM E
XMT
XMT E
RXPOL
RXPOL E
RCV
RCV E
LNK
LNK E
LNKST
output
LED1
LED3
LED
Interpretation Drive Enable Output Polarity
Figure 29. LED Control Logic
Link Status
Transmit
Receive
Default
Enabled
Enabled
Enabled
Default
Active LOW
Active LOW
Active LOW
Default
To
Pulse
Stretcher
18220C-31
P R E L I M I N A R Y
Am79C970
H_RESET will RESET all of or some portions of CSR0,
3, 4, 15, 58, 80, 82, 100, 112, 114, 122, 124 and 126 to
default values. H_RESET will RESET all of or some por-
tions of BCR 2, 4, 5, 6, 7, 18, 19, 20, 21 to default values.
H_RESET will reset the Command register in the PCI
configuration
microcode program to jump to its RESET state. Follow-
ing the end of the H_RESET operation, the PCnet-PCI
controller will attempt to read the EEPROM device
through the EEPROM Microwire interface. H_RESET
resets the T-MAU into the link fail state.
S_RESET
S_RESET = SOFTWARE_RESET is a PCnet-PCI RE-
SET operation that has been created by a read access
to the RESET REGISTER which is located at offset
14hex from the PCnet-PCI I/O base address.
S_RESET will RESET all of or some portions of CSR0,
3, 4, 15, 80, 100 and 124 to default values. S_RESET
will not affect any of the BCR and PCI configuration
space locations. S_RESET will cause the microcode
program to jump to its RESET state. Following the end
of the S_RESET operation, the PCnet-PCI controller
will NOT attempt to read the EEPROM device.
S_RESET sets the T-MAU into the link fail state.
Note that S_RESET will not cause a deassertion of the
REQ signal, if it happens to be active at the time of the
read to the reset register. The REQ signal will remain
active until the GNT signal is asserted. Following the
read of the RESET register, on the next clock cycle after
the GNT signal is asserted, the PCnet-PCI controller will
deassert the REQ signal. No bus master accesses will
have been performed during this brief bus ownership
period.
STOP
STOP is a PCnet-PCI RESET operation that has been
created by the ASSERTION of the STOP bit in CSR0.
That is, a STOP RESET is generated by writing a ONE
to the STOP bit of CSR0 when the STOP bit currently
has a value of ZERO. If the STOP bit value is currently a
ONE and a ONE is rewritten to the STOP bit, then NO
STOP RESET will be generated.
STOP will RESET all or some portions of CSR0, 3, and 4
to default values. STOP will not affect any of the BCR
and PCI configuration space locations. STOP will cause
the microcode program to jump to its RESET state. Fol-
lowing the end of the STOP operation, the PCnet-PCI
controller will NOT attempt to read the EEPROM device.
For the identity of individual CSRs and bit locations that
are affected by STOP, see the individual CSR register
descriptions. Setting the STOP bit does not affect
the T-MAU.
space.
H_RESET
will
cause
AMD
1-943
the