am79c970 Advanced Micro Devices, am79c970 Datasheet - Page 93

• Manufacturer Part Number: am79c970
• Description: Pcnettm-pci Single-chip Ethernet Controller For Pci Local Bus
• Manufacturer: Advanced Micro Devices

7–0
CSR8: Logical Address Filter, LADRF[15:0]
Bit
31–16 RES
15–0 LADRF[15:0]
CSR9: Logical Address Filter LADRF[31:16]
Bit
31–16 RES
15–0 LADRF[31:16] Logical
CSR10: Logical Address Filter, LADRF[47:32]
Bit
31–16 RES
15–0 LADRF[47:32] Logical
1-960
AMD
Name
Name
Name
RES
the PCnet-PCI controller initial-
zation routine.
Read accessible only when
STOP bit is set. Write operations
have no effect and should not be
performed. RLEN is only defined
after initialization. These bits are
unaffected by H_RESET, S_RE-
SET or STOP.
Reserved locations. Read as
ZERO. Write operations should
not be performed.
Description
Reserved locations. Written as
ZEROs and read as undefined.
Logical
LADRF[15:0]. The content of this
register is undefined until loaded
from the initialization block after
the INIT bit in CSR0 has been set
or a direct I/O write has been per-
formed on this register.
Read/write accessible only when
STOP bit is set. These bits are
unaffected
S_RESET or STOP.
Description
Reserved locations. Written as
ZEROs and read as undefined.
LADRF[31:16]. The content of
this register is undefined until
loaded from the initialization
block after the INIT bit in CSR0
has been set or a direct I/O write
has been performed on this
register.
Read/write accessible only when
STOP bit is set. These bits are
unaffected
S_RESET or STOP.
Description
Reserved locations. Written as
ZEROs and read as undefined.
LADRF[47:32]. The content of
this register is undefined until
loaded from the initialization
block after the INIT bit in CSR0
Address
Address
Address
by
by
H_RESET,
H_RESET,
P R E L I M I N A R Y
Filter,
Filter,
Filter,
Am79C970
CSR11: Logical Address Filter, LADRF[63:48]
Bit
31–16 RES
15–0 LADRF[63:48] Logical
CSR12: Physical Address Register, PADR[15:0]
Bit
31–16 RES
15–0 PADR[15:0]
CSR13: Physical Address Register, PADR[31:16]
Bit
31–16 RES
15–0 PADR[31:16]
Name
Name
Name
has been set or a direct I/O write
has been performed on this
register.
Read/write accessible only when
STOP bit is set. These bits are
unaffected
S_RESET or STOP.
Description
Reserved locations. Written as
ZEROs and read as undefined.
LADRF[63:48]. The content of
this register is undefined until
loaded from the initialization
block after the INIT bit in CSR0
has been set or a direct I/O write
has been performed on this
register.
Read/write accessible only when
STOP bit is set. These bits are
unaffected
S_RESET or STOP.
Description
Reserved locations. Written as
ZEROs and read as undefined.
Physical
PADR[15:0]. The content of this
register is undefined until loaded
from the initialization block after
the INIT bit in CSR0 has been set
or a direct I/O write has been per-
formed on this register.
Read/write accessible only when
STOP bit is set. These bits are
unaffected
S_RESET or STOP.
Description
Reserved locations. Written as
ZEROs and read as undefined.
Physical
PADR[31:16]. The content of this
register is undefined until loaded
from the initialization block after
the INIT bit in CSR0 has been set
or a direct I/O write has been per-
formed on this register.
Read/write accessible only when
STOP bit is set. These bits are
unaffected
S_RESET or STOP.
Address
Address
Address
by
by
by
by
H_RESET,
H_RESET,
H_RESET,
H_RESET,
Register,
Register,
Filter,