am79c970 Advanced Micro Devices, am79c970 Datasheet - Page 69

• Manufacturer Part Number: am79c970
• Description: Pcnettm-pci Single-chip Ethernet Controller For Pci Local Bus
• Manufacturer: Advanced Micro Devices

H_RESET default values. The content of the APROM
locations (offsets 0h – Fh from the I/O base address),
however, will not be cleared. The 8-bit checksum for the
entire 36 bytes of the EEPROM should be FFh.
If no EEPROM is present at the time of the automatic
read operation, then the PCnet-PCI controller will rec-
ognize this condition and will abort the automatic read
operation and reset both the PREAD and PVALID bits in
BCR19. All EEPROM-programmable BCR registers will
be assigned their default values after H_RESET. The
content of the Address PROM locations (offsets 0h – Fh
from the I/O base address) will be undefined.
If the user wishes to modify any of the configuration bits
that are contained in the EEPROM, then the seven com-
mand, data and status bits of BCR19 can be used to
write to the EEPROM. After writing to the EEPROM, the
host should set the PREAD bit of BCR19. This action
forces a PCnet-PCI controller re-read of the EEPROM
so that the new EEPROM contents will be loaded into
the EEPROM-programmable registers on board the
PCnet-PCI controller. (The EEPROM-programmable
registers may also be reprogrammed directly, but only
information that is stored in the EEPROM will be pre-
served at system power-down.) When the PREAD bit of
BCR19 is set, it will cause the PCnet-PCI controller to
terminate further accesses to internal I/O resources with
the PCI retry cycle. Accesses to the PCI configuration
space is still possible.
EEPROM Auto-Detection
The PCnet-PCI controller uses the EESK/LED1 pin to
determine if an EEPROM is present in the system. At all
rising CLK edges during the assertion of the RST pin,
the PCnet-PCI controller will sample the value of the
EESK/LED1 pin. If the sampled value is a ONE, then the
PCnet-PCI controller assumes that an EEPROM is pre-
sent, and the EEPROM read operation begins shortly
after the RST pin is deasserted. If the sampled value of
EESK/LED1 is a ZERO, then the PCnet-PCI controller
assumes that an external pulldown device is holding the
EESK/LED1 pin low, and therefore, there is no
EEPROM in the system. Note that if the designer cre-
ates a system that contains an LED circuit on the
EESK/LED1 pin but has no EEPROM present, then the
EEPROM auto-detection function will incorrectly con-
clude that an EEPROM is present in the system. How-
ever, this will not pose a problem for the PCnet-PCI
controller, since it will recognize the lack of an EEPROM
at the end of the read operation, when the checksum
verification fails.
Systems Without an EEPROM
Some systems may be able to save the cost of an
EEPROM by storing the ISO 8802-3 (IEEE/ANSI 802.3)
station address and other configuration information
somewhere else in the system. There are several de-
sign choices:
1-936
AMD
P R E L I M I N A R Y
Am79C970
In either case, following the PCI configuration, addi-
tional information, including the ISO 8802-3 (IEEE/ANSI
802.3) station address, may be loaded into the PCnet-
PCI controller. Note that the IESRWE bit (bit 8 of BCR2)
must be set before the PCnet-PCI controller will accept
writes to the APROM offsets within the PCnet-PCI I/O
resources map. Startup code in the system BIOS can
perform the PCI configuration accesses, the IESRWE
bit write, and the APROM writes.
Direct Access to the Microwire Interface
The user may directly access the Microwire port through
the EEPROM register, BCR19. This register contains
bits that can be used to control the Microwire interface
pins. By performing an appropriate sequence of I/O ac-
cesses to BCR19, the user can effectively write to and
read from the EEPROM. This feature may be used by a
system configuration utility to program hardware con-
figuration information into the EEPROM.
EEPROM-Programmable Registers
The following registers contain configuration informa-
tion that will be programmed automatically during the
EEPROM read operation:
1. I/O offsets 0h – Fh
2. BCR2
3. BCR16
4. BCR17
5. BCR18
6. BCR21
If the PREAD bit (BCR19) is reset to ZERO and the
PVALID bit (BCR19) is reset to ZERO, then the
EEPROM read has experienced a failure and the con-
tents of the EEPROM programmable BCR register will
be set to default H_RESET values. The content of the
APROM locations, however, will not be cleared.
If the LED1 is not needed in the system, then the sys-
tem designer may connect the EESK/LED1 pin to a
resistive pulldown device. This will indicate to the
EEPROM auto-detection function that no EEPROM
is present.
If the LED1 function is needed in the system, then the
system designer will connect the EESK/LED1 pin to
a resistive pullup device and the EEPROM auto-de-
tection function will incorrectly conclude that an
EEPROM is present in the system. However, this will
not pose a problem for the PCnet-PCI controller,
since it will recognize the lack of an EEPROM at the
end of the read operation, when the checksum verifi-
cation fails.
APROM locations
Miscellaneous Configuration
register
not used in the PCnet-PCI
controller
not used in the PCnet-PCI
controller
Burst Size and Bus Control
Register
Not Used