am79c970 Advanced Micro Devices, am79c970 Datasheet - Page 34

• Manufacturer Part Number: am79c970
• Description: Pcnettm-pci Single-chip Ethernet Controller For Pci Local Bus
• Manufacturer: Advanced Micro Devices

Descriptor DMA Transfers
PCnet-PCI microcode will determine when a descriptor
access is required. A descriptor DMA read will consist of
two DWORD (double-word) transfers. A descriptor
DMA write will consist of one or two DWORD transfers.
(The transfers within a descriptor DMA transfer master-
ship period will always be of the same type (either all
read or all write)).
If buffer chaining is used, writes to the descriptors of all
intermediate buffers consist of only one DWORD to
* Address values for AD[31:08] are constant throughout any single descriptor DMA transfer. AD[1:0] must be set to ZERO in the
During descriptor read accesses, the byte enable sig-
nals will indicate that all byte lanes are active. Should
some of the bytes not be needed, then the PCnet-PCI
controller will internally discard the extraneous informa-
tion that was gathered during such a read. During write
accesses, only the bytes which need to be written are
enabled, by activating the corresponding byte en-
able pins.
descriptor base address.
Sequence
Sequence
Bus Break
Bus Break
Address
Address
AD[7:0]*
AD[7:0]*
00
04
04
00
16-Bit Software Mode
16-Bit Software Mode
Item Accessed
Item Accessed
PCnet-ISA
MD1[15:0],
MD3[15:0],
PCnet-ISA
MD3[15:0],
MD1[15:0],
MD0[15:0]
MD2[15:0]
MD2[15:0]
MD0[15:0]
LANCE/
LANCE/
Table 2. Bus Master Writes to Descriptors
Table 1. Bus Master Reads of Descriptors
Item Accessed
Item Accessed
MD1[31:24],
MD1[31:24],
PCnet-PCI
MD2[15:0],
PCnet-PCI
MD2[15:0],
MD0[23:0]
MD1[15:0]
MD1[15:0]
MD0[23:0]
P R E L I M I N A R Y
Am79C970
return OWNership of the buffer to the system. On all sin-
gle buffer transmit or receive descriptors, as well as on
the last buffer in chain, writes to the descriptor consist of
two DWORDs. The first DWORD containing status in-
formation. The second DWORD containing additional
status and the OWNership bit (i.e. MD1[31]).
The transfers will be addressed as specified in tables 1
and 2.
The only significant differences between descriptor
DMA transfers and initialization DMA transfers are that
the addresses of the accesses follow different ordering.
Sequence
Sequence
Bus Break
Bus Break
Address
AD[7:0]*
Address
AD[7:0]*
04
00
08
04
32-Bit Software Mode
32-Bit Software Mode
Item Accessed
Item Accessed
PCnet-ISA
MD1[15:8],
PCnet-ISA
MD1[15:8],
MD2[15:0]
MD0[15:0]
MD3[15:0]
MD2[15:0]
MD1[7:0],
LANCE/
LANCE/
Item Accessed
Item Accessed
PCnet-PCI
PCnet-PCI
MD1[31:0]
MD0[31:0]
MD2[31:0]
MD1[31:0]
AMD
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