am79c970 Advanced Micro Devices, am79c970 Datasheet - Page 87

• Manufacturer Part Number: am79c970
• Description: Pcnettm-pci Single-chip Ethernet Controller For Pci Local Bus
• Manufacturer: Advanced Micro Devices

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AMD
RXON
TXON
INTR
IENA
completed. When IDON is set,
PCnet-PCI controller has read
the
memory.
When IDON is set, INTA is as-
serted if IENA = 1 and the mask
bit IDONM in CSR3 is clear.
IDON is set by the Buffer Man-
agement Unit after the initializa-
tion block has been read from
memory and cleared by writing a
“1”. Writing a “0” has no effect.
IDON is cleared by H_RESET or
S_RESET or by setting the
STOP bit.
Interrupt Flag indicates that one
or more following interrupt caus-
ing conditions has occurred:
BABL, MISS, MERR, MPCO,
RCVCCO, RINT, RPCO, TINT,
IDON, JAB or TXSTRT; and its
associated mask bit is clear. If
IENA = 1 and INTR is set, INTA
will be active.
INTR is read only. INTR is
cleared by H_RESET, S_RE-
SET, setting the STOP bit or by
clearing all of the active individ-
ual interrupt bits that have not
been masked out.
Interrupt Enable allows INTA to
be active if the Interrupt Flag is
set. If IENA = 0 then INTA will be
disabled regardless of the state
of INTR.
IENA is set by writing a “1” and
cleared by writing a “0”. IENA is
cleared by H_RESET or S_RE-
SET or by setting the STOP bit.
Receive On indicates that the
Receive function is enabled.
RXON is set if DRX = 0 in
CSR15[1] after the START bit is
set. If INIT and START are set to-
gether, RXON will not be set until
after the initialization block has
been read in.
RXON is read only. RXON is
cleared
S_RESET or by setting the
STOP bit.
Transmit On indicates that the
Transmit function is enabled.
TXON is set if DTX = 0
CSR15[1] after the START bit is
set. If INIT and START are set to-
gether, TXON will not be set until
after the initialization block has
been read in.
Initialization
by
H_RESET
block
P R E L I M I N A R Y
from
Am79C970
or
in
3
2
1
0
TDMD
STOP
STRT
INIT
TXON is read only. TXON is
cleared
S_RESET or by setting the
STOP bit.
Transmit Demand, when set,
causes the Buffer Management
Unit to access the Transmit De-
scriptor Ring without waiting for
the poll-time counter to elapse. If
TXON is not enabled, TDMD bit
will be reset and no Transmit De-
scriptor Ring access will occur.
TDMD is required to be set if the
DPOLL bit in CSR4 is set; setting
TDMD while DPOLL = 0 merely
hastens the PCnet-PCI control-
ler’s response to a Transmit De-
scriptor Ring Entry.
TDMD is set by writing a “1”. Writ-
ing a “0” has no effect. TDMD will
be cleared by the Buffer Manage-
ment Unit when it fetches a
Transmit Descriptor. TDMD is
cleared by H_RESET or S_RE-
SET and setting the STOP bit.
STOP assertion disables the chip
from all DMA activity. The chip
remains inactive until either
STRT or INIT are set. If STOP,
STRT and INIT are all set to-
gether, STOP will override STRT
and INIT.
STOP is set by writing a “1”, by
H_RESET or S_RESET. Writing
a “0” has no effect. STOP is
cleared by setting either STRT or
INIT.
STRT assertion enables PCnet-
PCI controller to send and re-
ceive frames, and perform buffer
management operations. Setting
STRT clears the STOP bit. If
STRT and INIT are set together,
PCnet-PCI controller initializa-
tion will be performed first.
STRT is set by writing a “1”. Writ-
ing a “0” has no effect. STRT is
cleared by H_RESET, S_RESET
or by setting the STOP bit.
INIT assertion enables PCnet-
PCI controller to begin the initiali-
zation procedure which reads in
the initialization block from mem-
ory. Setting INIT clears the STOP
bit. If STRT and INIT are set to-
gether, PCnet-PCI controller in-
itialization will be performed first.
INIT is not cleared when the
by
H_RESET
or