am79c970 Advanced Micro Devices, am79c970 Datasheet - Page 123

• Manufacturer Part Number: am79c970
• Description: Pcnettm-pci Single-chip Ethernet Controller For Pci Local Bus
• Manufacturer: Advanced Micro Devices

If a value other than those listed in the above table is de-
sired, CSR76 and CSR78 can be written after initializa-
tion is complete. See the description of the
appropriate CSRs.
When SSIZE32=1 (BCR20, bit 8), then the software
structures are defined to be 32 bits wide, and the RLEN
and TLEN fields in the initialization block are 4 bits wide,
occupying bits 23–20 (RLEN) and 31–28 (TLEN) and
the value in these fields determines the number of Re-
ceive and Transmit Descriptor Ring Entries (DRE)
which are used in the descriptor rings. Their meaning is
as follows:
1-990
AMD
47
R/TLEN
11XX
1X1X
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
Destination Address
Received Message
MATCH = 1:
MATCH = 0:
1 0
Packet Accepted
Packet Accepted
1
# of DREs
128
256
512
512
512
16
32
64
Figure 32. Address Match Logic
1
2
4
8
CRC
GEN
SEL
P R E L I M I N A R Y
Am79C970
If a value other than those listed in the above table is de-
sired, CSR76 and CSR78 can be written after initializa-
tion is complete. See the description of the appropriate
CSRs.
RDRA and TDRA
TDRA and RDRA indicate where the transmit and re-
ceive descriptor rings, respectively, begin. When
SSIZE32=1 (BCR20, bit 8), each DRE must be aligned
to a 16-byte boundary (TDRA [3:0]=0, RDRA [3:0]=0).
When SSIZE32=0 (BCR20, bit 8), each DRE must be
aligned to an 8-byte boundary (TDRA [2:0]=0, RDRA
[2:0]=0).
LADRF
The Logical Address Filter (LADRF) is a 64-bit mask that
is used to accept incoming Logical Addresses. If the first
bit in the destination address of the incoming frame (as
received from the wire) is a “1”, the address is deemed
logical. If the first bit is a “0”, it is a physical address and
is compared against the physical address that was
loaded through the initialization block.
A logical address is passed through the CRC generator,
producing a 32-bit result. The high order 6 bits of the
CRC is used to select one of the 64-bit positions in the
Logical Address Filter. If the selected filter bit is set, the
address is accepted and the frame is placed
into memory.
31
32-Bit Resultant CRC
26
64
6
63
25
MUX
Address Filter
(LADRF)
Logical
0
0
18220C-34
MATCH