am79c970 Advanced Micro Devices, am79c970 Datasheet - Page 80

• Manufacturer Part Number: am79c970
• Description: Pcnettm-pci Single-chip Ethernet Controller For Pci Local Bus
• Manufacturer: Advanced Micro Devices

USER ACCESSIBLE REGISTERS
The PCnet-PCI controller has three types of user regis-
ters: the PCI configuration registers, the Control and
Status registers (CSR) and the Bus Control registers
(BCR).
The PCnet-PCI controller implements all PCnet-ISA
(Am79C960) registers all LANCE (Am7990) registers,
all ILACC (Am79C900) registers, plus a number of addi-
tional registers. The PCnet-PCI controller CSRs are
compatible with both the PCnet-ISA (Am79C960) CSRs
and all of the LANCE (Am7990) CSRs upon power up.
Compatibility to the ILACC set of CSRs requires one ac-
cess to the Software Style register (BCR20, bits 7–0) to
be performed. By setting an appropriate value of the
Software Style register (BCR20, bits 7–0) the user can
select a set of CSRs that are compatible with the ILACC
set of CSRs.
The PCI configuration registers can be accessed in any
data width. All other registers must be accessed accord-
ing to the IO mode that is currently selected. When WIO
mode is selected, all other register locations are defined
to be 16 bits in width. When DWIO mode is selected, all
these register locations are defined to be 32 bits in
width, with the upper 16 bits of most register locations
marked as reserved locations with undefined values.
When performing register write operations in DWIO
mode, the upper 16 bits should always be written as ze-
ros, except for CSR88. When performing register read
operations in DWIO mode, the upper 16 bits of I/O re-
sources should always be regarded as having unde-
fined values, except for CSR88.
PCnet-PCI registers can be divided into four groups:
PCI Configuration Registers:
Registers that are intended to be initialized by the sys-
tem initialization procedure (e.g. BIOS device initializa-
tion routine) to program the operation of the PCnet-PCI
controller PCI bus interface.
Setup Registers:
Registers that are intended to be initialized by the device
driver to program the operation of various PCnet-PCI
controller features.
Running Registers:
Registers that are intended to be used by the device
driver software once the PCnet-PCI controller is running
to access status information and to pass control
information.
Test Registers:
Registers that are intended to be used only for testing
and diagnostic purposes.
Below is a list of the registers that fall into each of the first
three categories. Those registers that are not included
P R E L I M I N A R Y
Am79C970
in either of these lists can be assumed to be intended for
diagnostic purposes.
PCI Configuration Registers
The following is a list of those registers that would typi-
cally need to be programmed once during the initializa-
tion of the PCnet-PCI controller within a system
Setup Registers
The following is a list of those registers that would typi-
cally need to be programmed once during the setup of
the PCnet-PCI controller within a system. The control
bits in each of these registers typically do not need to be
modified once they have been written. However, there
are no restrictions as to how many times these registers
may actually be accessed. Note that if the default power
up values of any of these registers is acceptable to the
application, then such registers need never be ac-
cessed at all. Also note that some of these registers may
be programmable through the EEPROM read opera-
tion, and therefore do not necessarily need to be written
to by the system initialization procedure or by the
driver software.
Base Address register
Interrupt Line register
Status register
Command register
CSR1
CSR2
CSR3
CSR4
CSR8
CSR9
CSR10
CSR11
CSR12
CSR13
CSR14
CSR15
CSR24
CSR25
CSR30
CSR31
CSR47
CSR76
CSR78
CSR80
CSR82
CSR100
Initialization Address[15:0]
Initialization Address[31:16]
Interrupt Masks and Deferral Control
Test and Features Control
Logical Address Filter[15:0]
Logical Address Filter[31:16]
Logical Address Filter[47:32]
Logical Address Filter[63:48]
Physical Address Filter[15:0]
Physical Address Filter[31:16]
Physical Address Filter[47:32]
Mode Register
Base Address of Receive Ring Lower
Base Address of Receive Ring Upper
Base Address of Transmit Ring Lower
Base Address of Transmit Ring Upper
Polling Interval
Receive Ring Length
Transmit Ring Length
DMA Transfer Counter and FIFO
Threshold Control
Bus Activity Timer
Memory Error Timeout Register
AMD
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