am79c970 Advanced Micro Devices, am79c970 Datasheet - Page 107

• Manufacturer Part Number: am79c970
• Description: Pcnettm-pci Single-chip Ethernet Controller For Pci Local Bus
• Manufacturer: Advanced Micro Devices

11 – 1
0
CSR89: Chip ID Register Upper
Bit
31 – 16
15 – 12
11 – 0
CSR92: Ring Length Conversion
Bit
31–16 RES
15–0
CSR94: Transmit Time Domain
Reflectometry Count
Bit
31–16 RES
15–10 RES
9–0
1-974
AMD
XMTTDR
RCON
Name
Name
Name
Note that this code is not the
same as the Device ID in the PCI
configuration space.
Manufacturer ID. The 11-bit
manufacturer code for AMD is
00000000001. This code is per
the JEDEC Publication 106-A.
Note that this code is not the
same as the Vendor ID in the PCI
configuration space.
Always a logic 1.
Description
Reserved locations; Read as un-
defined.
Version. This 4-bit pattern is sili-
con-revision dependent.
Upper 12 bits of the PCnet-PCI
controller part number. i.e. 0010
0100 0011b.
Description
Reserved locations. Written as
ZEROs and read as undefined.
Ring Length Conversion Regis-
ter. This register performs a ring
length conversion from an en-
coded value as found in the in-
itialization block to a two’s
complement value used for inter-
nal counting. By writing bits
15–12 with an encoded ring
length, a Two’s complemented
value is read. The RCON register
is undefined until written.
Read/write accessible only when
STOP bit is set. These bits are
unaffected
S_RESET or STOP.
Description
Reserved locations. Written as
ZEROs and read as undefined.
Reserved locations. Read and
written as ZERO.
Time Domain Reflectometry re-
flects the state of an internal
counter that counts from the start
of transmission to the occurrence
by
H_RESET,
P R E L I M I N A R Y
Am79C970
CSR100: Bus Timeout
Bit
31–16 RES
15–0 MERRTO
CSR112: Missed Frame Count
Bit
31–16 RES
15–0
Name
Name
MFC
of loss of carrier. TDR is incre-
mented at a rate of 10 MHz.
Read accessible only when
STOP bit is set. Write operations
are ignored. XMTTDR is cleared
by H_RESET or S_RESET.
Description
Reserved locations. Written as
ZEROs and read as undefined.
This register contains the value
of the longest allowable bus la-
tency (interval between assertion
of REQ and assertion of GNT)
that a system may insert into a
PCnet-PCI
transfer. If this value of bus la-
tency is exceeded, then a MERR
will be indicated in CSR0, bit 11,
and an interrupt may be gener-
ated, depending upon the setting
of the MERRM bit (CSR3, bit 11)
and the IENA bit (CSR0, bit 6).
The value in this register is inter-
preted as the unsigned number
of XTAL1 clock periods divided 2.
(i.e., the value in this register is
given in 0.1
ments.) For example, the value
0200h (512 decimal) will cause a
MERR to be indicated after 51.2
microseconds of bus latency. A
value of ZERO will allow an infi-
nitely long bus latency; i.e. a
value of ZERO will never give a
bus timeout error.
This register is set to 0200h by
H_RESET or S_RESET and is
unaffected by STOP.
Read/write accessible only when
STOP bit is set.
Description
Reserved locations. Written as
ZEROs and read as undefined.
Missed Frame Count. Indicates
the number of missed frames.
MFC will roll over to a count of
ZERO from the value 65535.
The MPCO bit of CSR4 (bit 8) will
be set each time that this occurs.
controller
second incre-
master