ort82g5 Lattice Semiconductor Corp., ort82g5 Datasheet - Page 13

• Manufacturer Part Number: ort82g5
• Description: Xaui And Fc Fpscs
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
Dual Port RAMs
In addition to the backplane interface blocks, there are two independent memory blocks in the ASB. Each memory
block has a capacity of 4k words by 36 bits. It has one read port, one write port, and four byte-write-enable (active-
low) signals. The read data from the memory block is registered so that it works as a pipelined synchronous mem-
ory block.
FPSC Configuration
Configuration of the ORT42G5 and ORT82G5 occurs in two stages: FPGA bitstream configuration and embedded
core setup.
Prior to becoming operational, the FPGA goes through a sequence of states, including power up, initialization, con-
figuration, start-up, and operation. The FPGA logic is configured by standard FPGA bit stream configuration means
as discussed in the Series 4 FPGA data sheet.
After the FPGA configuration is complete, the options for the embedded core are set based on the contents of reg-
isters that are accessed through the FPGA system bus.
The system bus itself can be driven by an external PowerPC compliant microprocessor via the MPI block or via a
user master interface in FPGA logic. A simple IP block that drives the system by using the user register interface
and very little FPGA logic is available in the MPI/System Bus Technical Note. This IP block sets up the embedded
core via a state machine and allows the ORT42G5 and ORT82G5 to work in an independent system without an
external microprocessor interface.
Backplane Transceiver Core Detailed Description
The following sections describe the various logic blocks in the Embedded Core portion of the FPSC. The FPGA
section of the FPSC is identical to an ORCA OR4E04 FPGA except that the pads on one edge of the FPGA chip
are replaced by the Embedded Core. For a detailed description of the programmable logic functions, please see
the ORCA Series 4 FPGA Data Sheet and related application and technical notes.
The major functional blocks in the Embedded Core include:
• Two SERializer-DESerializer (SERDES) blocks and Clock and Data Recovery (CDR) circuitry
• 8b/10b encoder/decoders
• Transmit pre-emphasis circuitry
• 4-to-1 multiplexers (MUX) and 1-to-4 demultiplexers (DEMUX)
• Fibre channel synchronization state machine
• XAUI link alignment state machine
• Alignment FIFOs
• Embedded 4K x 36 RAM blocks (independent from transceiver logic).
A top level block diagram of the Embedded Core Logic is shown in Figure 2. The Embedded RAM blocks are not
shown. The external pins for the Embedded Core are listed later in this data sheet in Table 41 and the signals at the
Transceiver Embedded Core/FPGA interface for the ORT42G5 are listed in Table 8, Table 9 and Table 11; and for
the ORT82G5, in Table 8, Table 10 and Table 12.
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