ort82g5 Lattice Semiconductor Corp., ort82g5 Datasheet - Page 46

• Manufacturer Part Number: ort82g5
• Description: Xaui And Fc Fpscs
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Figure 26. Mixed Rate Transmit Clocking for a Single Block (Similar Connections Would Be Used for Block B)
Receive Clock Source Selection and Recommended Clock Distribution
In the receive path, one clock per bank of four channels, called RCK78[A:B], is sent to the FPGA logic. The control
register bits RCKSEL[0:1][A:B] are used to select the clock source for these clocks. The selection of the source for
RCK78[A:B] is controlled by these bits as shown in Table 18.
Table 18. RCK78[A:B] Source Selection
In the receive channel alignment bypass mode the data and recovered clocks for the eight channels (four per SER-
DES quad) are independent. The data for each channel are synchronized to the recovered clock from that channel.
Figure 27. - Receive Clocking for a Single Quad (Similar Connections Would Be Used for Quad B)
All Recovered
78.125 MHZ
FPGA
FPGA
Logic
Logic
Clocks at
78.125 MHz
50 MHz
÷
25 MHz
2
Channel AA Selected
as Clock Source
TSYS_CLK_AB
RCKSEL0
TSYS_CLK_AA
TSYS_CLK_AD
RSYS_CLK_A1
RSYS_CLK_A2
TSYS_CLK_AC
RWCKAA
RWCKAB
RWCKAC
RWCKAD
TCK78A
RCK78A
0
1
0
1
Common Logic, Quad A
Common Logic, Quad A
Channel AD
Channel AC
Channel AD
Channel AA
Channel AB
Channel AC
Channel AA
Channel AB
RCKSEL1
46
0
0
1
1
ORCA ORT42G5 and ORT82G5 Data Sheet
Clock Source
2
2
Channel C
Channel D
Channel A
Channel B
REFCLK[P:N]_A
100 MHz
REFCLK[P:N]_A
156.25 MHz
Outgoing Serial Data
Outgoing Serial Data
2.0 Gbps (Full-Rate)
1.0 Gbps (Half-Rate)
Two Channels of
Two Channels of
Incoming Serial Data
Four Channels of
3.125 Gbps