ort82g5 Lattice Semiconductor Corp., ort82g5 Datasheet - Page 53

• Manufacturer Part Number: ort82g5
• Description: Xaui And Fc Fpscs
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
• Parallel loopback at MUX/DEMUX boundary excluding SERDES (near end)
The three loopback modes are described in more detail in the following sections. As noted earlier, other specialized
loopback modes can be obtained by configuration of the FPGA logic or by connections external to the FPSC.
High-Speed Serial Loopback at the CML Buffer Interface
The high-speed serial loopback mode has the serial transmit signals looped back internally to the serial receive cir-
cuitry. The internal loopback path is from the input connection to the transmit CML buffer to the output connection
from the receive CML buffer. The data are sourced on the TWDxx[31:0], TCOMMAxx[3:0] and TBIT9xx[3:0] signal
lines and received on the MRWDxx[39:0] signal lines. The serial loopback path does not include the high-speed
input and output buffers. If TESTEN_xx is set, the HDOUTP_xx and HDOUTN_xx outputs are active in this mode
while the CML input buffers are powered down. The device is otherwise in its normal mode of operation. This mode
is normally used for tests where the data source and destination are on the same card and is the basic loopback
path shown earlier in Figure 32(a).
The data rate selection bits, TXHR and RXHR, in the channel configuration registers must be configured to carry
the same value. Table 19 and Table 20 summarize the settings of the control interface register configuration bits for
high-speed serial loopback.
Table 19. High-Speed Serial Loopback Configuration Bit Definitions for the ORT42G5
Table 20. High-Speed Serial Loopback Configuration Bit Definitions for the ORT82G5
30022, 30032, 30122,
30132
30023, 30033, 30123,
30133
30801, 30901
*This test mode can also be set using TESTEN_xx in place of LOOPENB_xx. In that case, Test Mode must be set to 00000.
30002, 30012, 30022,
30032, 30102, 30112,
30122, 30132
30003, 30013, 30023,
30033, 30103, 30113,
30123, 30133
Register
Address
Register
Address
Bit 2 = 1 (Channel C)
Bit 3 = 1 (Channel D)
Bit 0 = 0 or 1
Bit 7 = 0 or 1
Bit 0 = 0 or 1
Bit 3 = 0 or 1
Bit 0 = 0 or 1
Bit 7 = 0 or 1
Bit 0 = 0 or 1
Bit 3 = 0 or 1
Bit Value
Bit Value
LOOPENB_xx Set any of the bits 0-3 to 1 to do serial loopback on the corre-
Bit Name
Bit Name
8B10BR
8B10BR
8B10BT
8B10BT
RXHR
RXHR
TXHR
TXHR
53
Set to 0 or 1. TXHR and RXHR bits must be set to the same
value.
Set to 0 or 1. If set to 0, the 8b/10b encoder is excluded from
the loopback path. The 8b/10b encoder and decoder selec-
tion control bits must both be set to the same value.
Set to 0 or 1. TXHR and RXHR bits must be set to the same
value.
Set to 0 or 1. If set to 0, the 8b/10b decoder is excluded from
the loopback path. The 8b/10b encoder and decoder selec-
tion control bits must both be set to the same value.
sponding channel.* The high speed serial outputs will not be
active.
Set to 0 or 1. TXHR and RXHR bits must be set to the same
value.
Set to 0 or 1. If set to 0, the 8b/10b encoder is excluded from
the loopback path. The 8b/10b encoder and decoder selec-
tion control bits must both be set to the same value.
Set to 0 or 1. TXHR and RXHR bits must be set to the same
value.
Set to 0 or 1. If set to 0, the 8b/10b decoder is excluded from
the loopback path. The 8b/10b encoder and decoder selec-
tion control bits must both be set to the same value.
ORCA ORT42G5 and ORT82G5 Data Sheet
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