ort82g5 Lattice Semiconductor Corp., ort82g5 Datasheet - Page 5

• Manufacturer Part Number: ort82g5
• Description: Xaui And Fc Fpscs
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Programmable Features
• High-performance programmable logic:
• Traditional I/O selections:
• New programmable high-speed I/O:
• New capability to (de)multiplex I/O signals:
• Enhanced twin-block Programmable Function Unit (PFU):
• Abundant high-speed buffered and nonbuffered routing resources provide 2x average speed improvements over
• Hierarchical routing optimized for both local and global routing with dedicated routing resources. This results in
• SLIC provides eight 3-statable buffers, up to a 10-bit decoder, and PAL
• New 200 MHz embedded block-port RAM blocks, two read ports, two write ports, and two sets of byte lane
previous architectures.
faster routing times with predictable and efficient performance.
grammable logic cell.
enables. Each embedded RAM block can be configured as:
– 0.16 µm 7-level metal technology.
– Internal performance of >250 MHz.
– Over 400K usable system gates.
– Meets multiple I/O interface standards.
– 1.5V operation (30% less power than 1.8V operation) translates to greater performance.
– LVTTL (3.3V) and LVCMOS (2.5V and 1.8V) I/Os.
– Per pin-selectable I/O clamping diodes provide 3.3V PCI compliance.
– Individually programmable drive capability: 24 mA sink/12 mA source, 12 mA sink/6 mA source, or 6 mA
– Two slew rates supported (fast and slew-limited).
– Fast-capture input latch and input Flip-Flop (FF)/latch for reduced input setup time and zero hold time.
– Fast open-drain drive capability.
– Capability to register 3-state enable signal.
– Off-chip clock drive capability.
– Two-input function generator in output path.
– Single-ended: GTL, GTL+, PECL, SSTL3/2 (class I and II), HSTL (Class I, III, IV), ZBT, and DDR.
– Double-ended: LVDS, bused-LVDS, and LVPECL. Programmable (on/off) internal parallel termination (100
– New DDR on both input and output at rates up to 350 MHz (700 MHz effective rate).
– New 2x and 4x downlink and uplink capability per I/O (i.e., 50 MHz internal to 200 MHz I/O).
– Eight 16-bit Look-Up Tables (LUTs) per PFU.
– Nine user registers per PFU, one following each LUT, and organized to allow two nibbles to act indepen-
– New register control in each PFU has two independent programmable clocks, clock enables, local
– New LUT structure allows flexible combinations of LUT4, LUT5, new LUT6, 4 → 1 MUX, new 8 → 1 MUX,
– 32 x 4 RAM per PFU, configurable as single- or dual-port. Create large, fast RAM/ROM blocks (128 x 8 in
– Soft-Wired LUTs (SWL) allow fast cascading of up to three levels of LUT logic in a single PFU through fast
– Flexible fast access to PFU inputs from routing.
– Fast-carry logic and routing to all four adjacent PFUs for nibble-wide, byte-wide, or longer arithmetic func-
sink/3 mA source.
Ω ) is also supported for these I/Os.
dently, plus one extra for arithmetic operations.
SET/RESET, and data selects.
and ripple mode arithmetic functions in the same PFU.
only eight PFUs) using the Supplemental Logic and Interconnect Cell (SLIC) decoders as bank drivers.
internal routing which reduces routing congestion and improves speed.
tions, with the option to register the PFU carry-out.
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ORCA ORT42G5 and ORT82G5 Data Sheet
®
-like AND-OR-Invert (AOI) in each pro-