ort82g5 Lattice Semiconductor Corp., ort82g5 Datasheet - Page 29

• Manufacturer Part Number: ort82g5
• Description: Xaui And Fc Fpscs
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Figure 15. Alignment of all Eight SERDES Channels.
Note that any channel within an alignment group can be removed from that alignment group by setting
FMPU_STR_EN_xx to 0. The disabling of any channel(s) within an alignment group will not affect the operation of
the remaining active channels. If the active channels are synchronized, that synchronization will be maintained and
no data loss will occur.
For every alignment group, there are both an OVFL and an OOS status register bit. The OVFL bit is set when align-
ment FIFO overflow occurs. The OOS bit is flagged when the down counter in the synchronization algorithm has
reached a value of 0 and alignment characters from all channels within an alignment group have not been received.
In the memory map section for the ORT42G5 the bits indicating OOS and OVFL are referred to as
SYNC2_[A:B]_OOS and SYNC4_OOS and the bits indicating OVFL are SYNC2_[A:B]_OVFL and SYNC4_OVFL.
In the memory map section for the ORT82G5, the bits indicating OOS and OVFL are referred to as
SYNC2_[A1,A2,B1,B2]_OOS, SYNC4_[A:B]_OOS and SYNC8_OOS and the bits indicating OVFL are
SYNC2_[A1,A2,B1,B2]_OVFL, SYNC4_[A:B]_OVFL and SYNC8_OVFL.
Alignment can also be done between the receive channels on two ORT82G5 devices. Each of the two devices
needs to provide its aligned K_CTRL or other alignment character to the other device, which will delay reading from
a second alignment FIFO until all channels requesting alignment on the current device and all channels requesting
alignment on the other device are aligned (as indicated on the K_CTRL character). These second alignment FIFOs
will be implemented in FPGA logic on the ORT82G5. This scheme also requires that the reference clock for both
devices be driven by the same signal.
XAUI Lane Alignment Function (Lane Deskew)
In XAUI mode, the receive section in each lane uses the /A/ code group to compensate for lane-to-lane skew. The
mechanism restores the timing relationship between the 4 lanes by lining up the /A/ characters into a column.
Figure 16 shows the alignment of four lanes based on /A/ character. A minimum spacing of 16 code-groups implies
that at least ± 80 bits of skew compensation capability should be provided, which the devices significantly exceed.
Channel BA
Channel BD
Channel AB
Channel AA
Channel BB
Channel AD
Channel BC
Channel AC
29
ORCA ORT42G5 and ORT82G5 Data Sheet
Channel AA
Channel AB
Channel AC
Channel AD
Channel BA
Channel BB
Channel BC
Channel BD
t
0