ort82g5 Lattice Semiconductor Corp., ort82g5 Datasheet - Page 69

• Manufacturer Part Number: ort82g5
• Description: Xaui And Fc Fpscs
• Manufacturer: Lattice Semiconductor Corp.

Table 30. ORT82G5 Memory Map (Continued)
Lattice Semiconductor
30003 - AA
30013 - AB
30023 - AC
30033 - AD
30103 - BA
30113 - BB
30123 - BC
30133 - BD
SERDES Common Transmit and Receive Channel Configuration Registers (Read/Write), xx=[AA,...,BD]
30004 - AA
30014 - AB
30024 - AC
30034 - AD
30104 - BA
30114 - BB
30124 - BC
30134 - BD
Absolute
Address
(0x)
[5:7]
[3:6]
Bit
[0]
[1]
[2]
[3]
[4]
[0]
[1]
[2]
[7]
RXHR_xx
PWRDNR_xx
Reserved
8b10bR_xx
LINKSM_xx
Not used
Reserved
MASK_xx
SWRST_xx
Not used
TESTEN_xx
Name
descrip.
Reset
Value
(0x)
See
20
bit
Receive Half Rate Selection Bit, Channel xx. When RXHR_xx =1,
HDIN_xx's baud rate = (REFCLK[A:B]*10) and RCK78[A:B]=(REF-
CLK[A:B]/4); when RXHR_xx=0, HDIN_xx's baud rate = (REF-
CLK[A:B]*20) and RCK78[A:B]=(REFCLK/2). RXHR_xx = 0 on device
reset.
Receiver Power Down Control Bit, Channel xx. When PWRDNR_xx = 1,
sections of the receive hardware are powered down to conserve power.
PWRDNR_xx = 0 on device reset.
Reserved. Set to 1 on device reset.
Receive 8b/10b Decoder Enable Bit, Channel xx. When 8b10bR = 1, the
8b/10b decoder in the receive path is enabled. Otherwise, the data is
passed undecoded. 8b10bR_xx = 0 on device reset.
Link State Machine Enable Bit, Channel xx. When LINKSM_xx = 1, the
receiver Fiber Channel link state machine is enabled. Otherwise, the
Fibre Channel link state machine is disabled.
Note: LINKSM_xx is ignored when XAUI_MODE_xx=1. LINKSM_xx = 0
on device reset.
Not used.
Reserved, must be set to 0. Set to 0 on device reset.
Transmit and Receive Alarm Mask Bit, Channel xx. When MASK_xx = 1,
the transmit and receive alarms of a channel are prevented from gener-
ating an interrupt (i.e., they are masked or disabled). The MASK_xx bit
overrides the individual alarm mask bits in the Alarm Mask Registers.
MASK_xx = 1 on device reset.
Transmit and Receive Software Reset Bit, Channel xx. When
SWRST_ss = 1, this bit provides the same function as the hardware
reset, except that all configuration register settings are unaltered. This is
not a self-clearing bit. Once set, this bit must be manually set and
cleared. SWRST = 0 on device reset.
Not used. 0 on reset.
Transmit and Receive Test Enable Bit, Channel xx. When TESTEN_xx =
1, the transmit and receive sections are placed in test mode. The
TestMode_[A:B][4:0] bits in the Global Control Registers specify the par-
ticular test, and must also be set.
Note: When the global test enable bit GTESTEN_[A:B] = 0, the individual
channel test enable bits are used to selectively place a channel in test or
normal mode. When GTESTEN_[A:B] = 1, all channels are set to test
mode regardless of their TESTEN setting. TESTEN_xx = 0 on device
reset.
69
ORCA ORT42G5 and ORT82G5 Data Sheet
Description